Fully-depleted son
View Patent ↗A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.
1. A semiconductor device, comprising:
a semiconductor substrate;
an insulating layer on the semiconductor substrate;
a first semiconductor layer disposed on the insulating layer;
a dielectric layer disposed on a portion of the first semiconductor layer;
a second semiconductor layer disposed around the dielectric layer;
a source and drain junction disposed within the second semiconductor layer;
a gate disposed on a portion of the second semiconductor layer; and
a spacer disposed around the gate and covering a portion of the second semiconductor layer.
2. The semiconductor device of claim 1 , wherein the first semiconductor layer has a thickness from about 10 nanometers to about 30 nanometers.
3. The semiconductor device of claim 1 , wherein the second semiconductor layer is made of a material selected from the group consisting of: silicon, germanium, a compound of a Group III/V elements, a compound of a Group II/VI elements, and a combination thereof.
4. The semiconductor device of claim 1 , wherein the second semiconductor layer has a thickness of about 2 nanometers to about 10 nanometers.
5. The semiconductor device of claim 1 , wherein the dielectric layer is a single-layer dielectric.
6. The semiconductor device of claim 1 , wherein the dielectric layer is a multi-layer dielectric.
7. The semiconductor device of claim 1 , wherein the dielectric layers has a thickness of about 10 nanometers to about 25 nanometers.
8. The semiconductor device of claim 1 , wherein there is an implant for junction butting disposed beneath the source and drain junction.
9. The semiconductor device of claim 1 , wherein the dielectric layer is about 3 nanometers to about 5 nanometers shorter than the length of the gate.
10. The semiconductor device of claim 1 , wherein the first semiconductor layer is a silicon-on-insulator layer.
11. The semiconductor device of claim 1 , wherein the dielectric layer is made of a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and a high-k dielectric.
12. The semiconductor device of claim 1 , wherein the gate comprises at least one gate dielectric layer and at least one gate conducting layer.