APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY
A memory layer in a three-dimensional memory array is provided. The memory layer includes a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias, and a plurality of memory cells operatively coupled to the memory lines. Numerous other aspects are disclosed.
1 . A memory layer in a three-dimensional memory array, the memory layer comprising:
a plurality of memory lines and vias formed by a damascene process using an imprint lithography template having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias; and
a plurality of memory cells operatively coupled to the memory lines.
2 . The memory layer of claim 1 , wherein the imprint lithography template is formed from at least one of quartz and fused silica.
3 . The memory layer of claim 1 , wherein the template includes a plurality of rails corresponding to trenches for a plurality of memory lines.
4 . The memory layer of claim 1 , wherein the template includes a plurality of pillars corresponding to holes for a plurality of vias.
5 . The memory layer of claim 1 , wherein the template includes a plurality of pillars corresponding to holes for a plurality of vias and a plurality of rails corresponding to trenches for a plurality of memory lines.
6 . The memory layer of claim 5 , wherein the template includes the pillars disposed on the rails.
7 . The memory layer of claim 6 , wherein the pillars disposed on the rails are disposed on alternate opposite ends of each adjacent rail.
8 . The memory layer of claim 6 , wherein the pillars disposed on the rails have a combined height greater than a height of the rails alone.
9 . The memory layer of claim 1 , wherein the template includes a plurality of landings corresponding to contact pads.
10 . The memory layer of claim 1 , wherein the template includes a plurality of pillars corresponding to holes for vias, a plurality of rails corresponding to trenches for memory lines, and a plurality of landings corresponding to contact pads.
11 . The memory layer of claim 10 , wherein the template includes a landing at alternate opposite ends of each adjacent rail.
12 . The memory layer of claim 10 , wherein the template includes the pillars disposed on the landings.
13 . The memory layer of claim 1 , wherein the template includes a plurality of pillars wherein at least some of the pillars include at least one shoulder.
14 . The memory layer of claim 13 , wherein the template includes a plurality of pillars with shoulders disposed at a depth different that the depths corresponding to the memory lines and the vias.
15 . The memory layer of claim 1 , wherein the memory layer is formed by imprinting the template into a transfer material that includes resist.
16 . The memory layer of claim 1 , wherein the memory layer is formed using a layer of transfer material deposited on a hardmask layer which is deposited on a dielectric layer which is deposited on a wire layer.
17 . An imprint lithography mask for manufacturing a memory layer in a three dimensional memory, the mask comprising:
a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths,
wherein at least one imprint depth corresponds to trenches for forming memory lines and wherein at least one depth corresponds to holes for forming vias.
18 . The imprint lithography mask of claim 17 , wherein the imprint lithography mask is formed from at least one of quartz and fused silica.
19 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of rails corresponding to the trenches for a plurality of memory lines.
20 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of pillars corresponding to holes for a plurality of vias.
21 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of pillars corresponding to holes for a plurality of vias and a plurality of rails corresponding to trenches for a plurality of memory lines.
22 . The imprint lithography mask of claim 21 , wherein the mask includes the pillars disposed on the rails.
23 . The imprint lithography mask of claim 22 , wherein the pillars disposed on the rails are disposed on alternate opposite ends of each adjacent rail.
24 . The imprint lithography mask of claim 22 , wherein the pillars disposed on the rails have a combined height greater than a height of the rails alone.
25 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of landings corresponding to contact pads.
26 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of pillars corresponding to holes for vias, a plurality of rails corresponding to trenches for memory lines, and a plurality of landings corresponding to contact pads.
27 . The imprint lithography mask of claim 26 , wherein the mask includes a landing at alternate opposite ends of each adjacent rail.
28 . The imprint lithography mask of claim 27 , wherein the mask includes the pillars disposed on the landings.
29 . The imprint lithography mask of claim 17 , wherein the mask includes a plurality of pillars wherein at least some of the pillars include at least one shoulder.
30 . The imprint lithography mask of claim 29 , wherein the mask includes a plurality of pillars with shoulders disposed at a depth different that the depths corresponding to the memory lines and the vias.
31 . The imprint lithography mask of claim 17 , wherein the mask is adapted to concurrently form memory lines and vias for a memory layer by imprinting the mask into a transfer material that includes resist.
32 . The imprint lithography mask of claim 17 , wherein the mask is adapted to form a memory layer from a layer of transfer material deposited on a hardmask layer which is deposited on a dielectric layer which is deposited on a wire layer.
33 . A three dimensional memory array comprising:
a plurality of horizontal memory layers formed on top of each other and electrically coupled to each other by vertical zias, the zias formed from aligned vias in each memory layer, and the memory layers including a plurality of memory lines and the vias, both formed concurrently using an imprint lithography mask.
34 . The three dimensional memory array of claim 33 , wherein the plurality of memory lines and vias are formed by a damascene process using the imprint lithography mask having a plurality of depths, wherein at least one depth corresponds to the memory lines and wherein at least one depth corresponds to the vias.
35 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask is formed from at least one of quartz and fused silica.
36 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of rails corresponding to trenches for a plurality of memory lines.
37 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of pillars corresponding to holes for a plurality of vias.
38 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of pillars corresponding to holes for a plurality of vias and a plurality of rails corresponding to trenches for a plurality of memory lines.
39 . The three dimensional memory array of claim 38 , wherein the imprint lithography mask includes the pillars disposed on the rails.
40 . The three dimensional memory array of claim 39 , wherein the pillars disposed on the rails are disposed on alternate opposite ends of each adjacent rail.
41 . The three dimensional memory array of claim 39 , wherein the pillars disposed on the rails have a combined height greater than a height of the rails alone.
42 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of landings corresponding to contact pads.
43 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of pillars corresponding to holes for vias, a plurality of rails corresponding to trenches for memory lines, and a plurality of landings corresponding to contact pads.
44 . The three dimensional memory array of claim 43 , wherein the imprint lithography mask includes a landing at alternate opposite ends of each adjacent rail.
45 . The three dimensional memory array of claim 44 , wherein the imprint lithography mask includes the pillars disposed on the landings.
46 . The three dimensional memory array of claim 33 , wherein the imprint lithography mask includes a plurality of pillars wherein at least some of the pillars include at least one shoulder.
47 . The three dimensional memory array of claim 46 , wherein the imprint lithography mask includes a plurality of pillars with shoulders disposed at a depth different that the depths corresponding to the memory lines and the vias.
48 . The three dimensional memory array of claim 33 , wherein the memory layers are formed by imprinting the imprint lithography mask into a transfer material that includes resist.
49 . The three dimensional memory array of claim 33 , wherein the memory layers are formed using a layer of transfer material deposited on a hardmask layer which is deposited on a dielectric layer which is deposited on a wire layer.