Embedded magnetic random access memory (MRAM)
View Patent ↗A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.
1. A method of manufacturing a magnetic random access memory (MRAM) cell comprising:
forming a plurality of diffusion regions and a transistor gate, collectively defining an access transistor, in a silicon substrate;
forming a plurality of metal-interposed-in-interlayer dielectric (ILD) layers on top of a first ILD layer with each of the plurality of ILD layers being formed on top of a previous layer of the plurality of ILD layer, each of the plurality of ILD layers having metal dispersed therethrough, on top of the access transistor, the first ILD positioned on top of the diffusion regions;
forming a magneto tunnel junction (MTJ) substantially on top of the plurality of ILD layers, each of the plurality of ILD layers having the metal dispersed therethrough, a bit line positioned in close proximity to the MTJ;
forming a spacer on top of and around the MTJ; and
depositing a metal on top of the bit line and over a portion of the top most one of the plurality of ILD layers and extending over the top of the MTJ.
2. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is made of silicon nitride.
3. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is approximately 1,500 Angstroms in thickness.
4. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein the spacer is made of oxide.
5. The method of manufacturing a magnetic random access memory (MRAM) cell, as recited in claim 1 , wherein more than one embedded MRAM is formed on the silicon substrate.
6. A method of manufacturing a magnetic random access memory (MRAM) cell comprising: forming an access transistor on top of a silicon substrate; forming an embedded MRAM on a plurality of metal-interposed-in-interlayer dielectric (ILD) layers, each of the plurality of ILD layers including metal dispersed there through and including a first magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line, an MTJ mask is used to pattern the MTJ and is etched to expose the MTJ, ultimately, metal is formed on top of the bit line and extended to contact the MTJ.