Data storage system with dynamic read threshold mechanism and method of operation thereof

1. A method of operation of a data storage system comprising:

determining a middle read threshold for a memory die;

calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and

reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

2. The method as claimed in claim 1 further comprising:

retrieving a die read threshold from a controller database;

calculating an outlier block offset for an outlier block based on the location of the outlier block; and

modifying the lower read threshold, the middle read threshold, and the upper read threshold with the outlier block offset.

3. The method as claimed in claim 1 further comprising:

retrieving a die read threshold from a controller database;

calculating an outlier page offset for an outlier page based on the location of the outlier page; and

modifying the lower read threshold, the middle read threshold, and the upper read threshold with the outlier page offset.

4. The method as claimed in claim 1 further comprising modifying the lower read threshold, the middle read threshold, and the upper read threshold based on a retention time.

5. The method as claimed in claim 1 further comprising modifying the lower read threshold, the middle read threshold, and the upper read threshold based on a read disturb count.

6. A method of operation of a data storage system comprising:

determining a middle read threshold for a memory die;

determining a memory element age for the memory die;

calculating a lower read threshold and an upper read threshold based on the middle read threshold and the memory element age; and

reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

7. The method as claimed in claim 6 further comprising:

detecting a power up event;

detecting a first test threshold having a bit error rate after detecting the power up event;

detecting a second test threshold having another of the bit error rate greater than the bit error rate of the first test threshold, the second test threshold lower than the first test threshold;

determining a power up offset for a memory die based on the first test threshold; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the power up offset.

8. The method as claimed in claim 6 further comprising:

detecting a scheduling event based on a program erase cycle count meeting or exceeding a program erase cycle count threshold; and

in accordance with detection of the scheduling event:

calculating a program erase offset based on the program erase cycle count; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the program erase offset.

9. The method as claimed in claim 6 further comprising:

detecting a scheduling event based on an error count meeting or exceeding an error count threshold; and

in accordance with detection of the scheduling event:

calculating an error count offset based on the error count; and

modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the error count offset.

10. The method as claimed in claim 6 , including setting the memory element age to a program erase cycle count.

11. A data storage system comprising:

a memory die;

a controller, coupled to the memory die controlling operation of the data storage system, the controller including:

a mapping module for determining a middle read threshold for the memory die;

one or more modules for calculating a lower read threshold and an upper read threshold based on the middle read threshold and a memory element age; and

a memory interface, coupled to the memory die, for reading a memory page of the memory die using the lower read threshold, the middle read threshold, or the upper read threshold for compensating for a charge variation.

12. The system as claimed in claim 11 , wherein the controller further comprises:

a controller database for retrieving a die read threshold; and

an outlier block adjustment module, coupled to the control unit, for calculating an outlier block offset for an outlier block based on the location of the outlier block and for modifying the lower read threshold, the middle read threshold, or the upper read threshold with the outlier block offset.

13. The system as claimed in claim 11 , wherein the controller further comprises:

a controller database for retrieving a die read threshold; and

an outlier page adjustment module for calculating an outlier page offset for an outlier page based on the location of the outlier page and for modifying the lower read threshold, the middle read threshold, or the upper read threshold with the outlier page offset.

14. The system as claimed in claim 11 wherein the lower read threshold, the middle read threshold, or the upper read threshold are modified based on a retention time.

15. The system as claimed in claim 11 wherein the lower read threshold, the middle read threshold, or the upper read threshold are modified based on a read disturb count.

16. The system as claimed in claim 11 , wherein the controller further comprises a module for retrieving the memory element age of the memory die.

17. The system as claimed in claim 16 , wherein the controller further comprises:

a power up event module for detecting a power up event;

a find read thresholds module, coupled to the power up event module, for detecting a first test threshold having a bit error rate and for detecting a second test threshold having another of the bit error rate greater than the bit error rate of the first test threshold with the second test threshold lower than the first test threshold; and

a calculate power up offset module, coupled to the find read thresholds module, for determining a power up offset for the memory die based on the first test threshold and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the power up offset.

18. The system as claimed in claim 16 , wherein the controller further comprises:

a program erase event module for detecting a scheduling event based on a program erase cycle count meeting or exceeding a program erase cycle count threshold; and

a calculate program erase offset module, coupled to the program erase event module, for calculating a program erase offset based on the program erase cycle count and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the program erase offset.

19. The system as claimed in claim 16 , wherein the controller further comprises:

an error count event module for detecting a scheduling event based on an error count meeting or exceeding an error count threshold; and

an calculate error count offset module, coupled to the error count event module, for calculating an error count offset based on the error count and for modifying the lower read threshold, the middle read threshold, or the upper read threshold based on the error count offset.

20. The system as claimed in claim 16 , wherein the controller further comprises an initial mapping module for setting the memory element age to the program erase cycle count.