IP Library Granted Patent US 9,054,218
Granted Patent B2
US 9,054,218 · App. 13/961,248 · Granted Jun 9, 2015

Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same

Inventors: Thomas N. Adam (Slingerlands, NY); Kangguo Cheng (Schenectady, NY); Bruce B. Doris (Slingerlands, NY); Hong He (Schenectady, NY); Ali Khakifirooz (Mountain View, CA); Alexander Reznicek (Troy, NY)
Assignee: International Business Machines Corporation
H01L21/823821H01L27/0924H01L29/6681H01L27/0886H01L29/66795H01L27/1211H01L21/845H01L21/823431
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Quick Facts
Patent No.
US 9,054,218
App. No.
13/961,248
Granted
Jun 9, 2015
Kind
B2
Abstract

A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors.

Claims (57)

1. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate;

epitaxially growing a sacrificial epitaxy region between the fins;

stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins; and

forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors; and

removing a portion of the dielectric layer corresponding to a first transistor to form an opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending from fins of the first transistor, wherein the opening is over an entire merged epitaxial shape between at least two neighboring fins, and over each of the at least two neighboring fins.

2. The method according to claim 1 , wherein the sacrificial epitaxy region between fins of a same transistor merges the fins with each other.

3. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate;

epitaxially growing a sacrificial epitaxy region between the fins;

stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins;

forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors;

removing a portion of the dielectric layer corresponding to a first transistor to form an opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending from fins of the first transistor; and

removing the sacrificial epitaxy region extending from the fins of the first transistor.

4. The method according to claim 3 , wherein a sacrificial epitaxy region extending from fins of a second transistor remains covered by the dielectric layer during removal of the sacrificial epitaxy region extending from the fins of the first transistor.

5. The method according to claim 3 , further comprising growing an epitaxy region for the first transistor in a space previously occupied by the removed sacrificial epitaxy region.

6. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate;

epitaxially growing a sacrificial epitaxy region between the fins;

stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins;

forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors;

removing a portion of the dielectric layer corresponding to a first transistor to form an opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending from fins of the first transistor; and

removing the sacrificial epitaxy region extending from the fins of the first transistor;

wherein a sacrificial epitaxy region extending from fins of a second transistor remains covered by the dielectric layer during removal of the sacrificial epitaxy region extending from the fins of the first transistor; and

wherein the first and second transistors are doped differently.

7. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate;

epitaxially growing a sacrificial epitaxy region between the fins;

stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins;

forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors;

removing a portion of the dielectric layer corresponding to a first transistor to form an opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending from fins of the first transistor;

removing the sacrificial epitaxy region extending from the fins of the first transistor;

growing an epitaxy region for the first transistor in a space previously occupied by the removed sacrificial epitaxy region; and

overgrowing the epitaxy region for the first transistor.

8. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a plurality of fins on a substrate;

epitaxially growing a sacrificial epitaxy region between the fins;

stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins;

forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors;

removing a portion of the dielectric layer corresponding to a first transistor to form an opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending from fins of the first transistor;

removing the sacrificial epitaxy region extending from the fins of the first transistor;

growing an epitaxy region for the first transistor in a space previously occupied by the removed sacrificial epitaxy region; and

depositing a dielectric layer on the epitaxy region for the first transistor.

9. The method according to claim 8 , further comprising removing a portion of the dielectric layer corresponding to a second transistor to form a second opening in the dielectric layer exposing at least part of the sacrificial epitaxy region extending front fins of the second transistor.

10. The method according to claim 9 , further comprising removing the sacrificial epitaxy region extending from the fins of the second transistor.

11. The method according to claim 10 , wherein the epitaxy region for the first transistor remains covered by the dielectric layer during removal of the sacrificial epitaxy region extending from fins of the second transistor.

12. The method according to claim 11 , wherein the first and second transistors are doped differently.

13. The method according to claim 10 , further comprising growing an epitaxy region for the second transistor in a space previously occupied by the removed sacrificial epitaxy region from the second transistor.

14. The method according to claim 13 , further comprising overgrowing the epitaxy region for the second transistor.

15. A method for manufacturing a fin field-effect transistor (FinFET) device, the method comprising:

forming a first plurality of fins on a substrate corresponding to a first transistor;

forming a second plurality of fins on the substrate corresponding to a second transistor;

epitaxially growing a sacrificial epitaxy region between the first plurality of fins corresponding to the first transistor and between the second plurality of fins corresponding to the second transistor;

stopping growth of the sacrificial epitaxy region to avoid contact of the sacrificial epitaxy region between the first plurality of fins and the second plurality of fins;

forming a dielectric layer on the substrate between the sacrificial epitaxy region extending from adjacent fins of the first and second transistors; and

removing the sacrificial epitaxy region extending from the fins of the first transistor and extending from fins of the second transistor.

16. The method according to claim 15 , further comprising growing a first epitaxy region for the first transistor and a second epitaxy region for the second transistor in a space previously occupied by the removed sacrificial epitaxy region.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2013
From: ADAM, THOMAS N.; CHENG, KANGGUO; DORIS, BRUCE B.; HE, HONG; KHAKIFIROOZ, ALI; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030961/0630 →
Continuity (1)
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