Techniques for selecting a predicted indirect branch address from global and local caches

1. A method of branch target prediction, comprising:

storing, based on an instruction fetch address for a group of fetched instructions, first predicted targets for first indirect branch instructions in respective entries of a local count cache;

storing, based on the instruction fetch address and a global history vector for the instruction fetch address, second predicted targets for second indirect branch instructions in respective entries of a global count cache; and

selecting one of the local count cache and the global count cache to provide a selected predicted target for an indirect branch instruction in the group of fetched instructions;

wherein the selecting one of the local count cache and the global count cache to provide the selected predicted target is based on a selector associated with one of the first and second predicted targets;

the method further comprising:

updating the selector to move the selector toward the selected predicted target when a non-selected predicted target is incorrect and the selected predicted target is correct;

updating the selector to move the selector toward the non-selected predicted target when the selected predicted target is incorrect and the non-selected predicted target is correct; and

maintaining the selector when the selected predicted target and the non-selected predicted target are both correct or when the selected predicted target and the non-selected predicted target are both incorrect.

2. The method of claim 1 , further comprising:

selecting an entry from the local count cache based on the instruction fetch address for the group of fetched instructions; and

storing a first predicted target from the selected entry in the local count cache in an associated local count cache register.

3. The method of claim 2 , further comprising:

selecting an entry from the global count cache based on the instruction fetch address and the global history vector; and

storing a second predicted target from the selected entry in the global count cache in an associated global count cache register.

4. The method of claim 3 , further comprising:

exclusive ORing the instruction fetch address with the global history vector to provide an index; and

selecting the entry in the global count cache based on the index.

5. The method of claim 3 , further comprising:

selecting one of the local count cache register and the global count cache register to provide the selected predicted target based on the selector associated with one of the first and second predicted targets.

6. The method of claim 5 , further comprising:

updating, based on whether the first predicted target was determined to be a correct target following execution of the indirect branch instruction, a first count associated with the first predicted target in the local count cache.

7. The method of claim 6 , further comprising:

incrementing the first count in response to the first predicted target being the correct target; and

decrementing the first count in response to the first predicted target not being the correct target.

8. The method of claim 5 , further comprising:

updating, based on whether the second predicted target was determined to be a correct target following execution of the indirect branch instruction, a second count associated with the second predicted target in the global count cache.

9. The method of claim 8 , further comprising:

incrementing the second count in response to the second predicted target being the correct target; and

decrementing the second count in response to the second predicted target not being the correct target.

10. The method of claim 6 , further comprising:

maintaining the entry associated with the second predicted target in the global count cache when the local count cache is selected and the first count is above a predetermined value; and

replacing the entry in the global count cache when the local count cache is selected and the first count is below the predetermined value.

11. The method of claim 1 , wherein at least some of the first and second predicted targets are the same.

12. A processor, comprising:

a cache memory; and

a processor core coupled to the cache memory, wherein the processor core is configured to:

store, based on an instruction fetch address for a group of fetched instructions, first predicted targets for first indirect branch instructions in respective entries of a local count cache;

store, based on the instruction fetch address and a global history vector for the instruction fetch address, second predicted targets for second indirect branch instructions in respective entries of a global count cache; and

select one of the local count cache and the global count cache to provide a selected predicted target for an indirect branch instruction in the group of fetched instructions;

wherein the selecting one of the local count cache and the global count cache to provide the selected predicted target is based on a selector associated with one of the first and second predicted targets; and

wherein the processor core is further configured to:

update the selector to move the selector toward the selected predicted target when a non-selected predicted target is incorrect and the selected predicted target is correct;

update the selector to move the selector toward the non-selected predicted target when the selected predicted target is incorrect and the non-selected predicted target is correct; and

maintain the selector when the selected predicted target and the non-selected predicted target are both correct or when the selected predicted target and the non-selected predicted target are both incorrect.

13. The processor of claim 12 , wherein the processor core is further configured to:

select an entry from the local count cache based on the instruction fetch address for the group of fetched instructions;

store a first predicted target from the selected entry in the local count cache in an associated local count cache register;

select an entry from the global count cache based on the instruction fetch address and the global history vector; and

store a second predicted target from the selected entry in the global count cache in an associated global count cache register.

14. The processor of claim 13 , wherein the processor core is further configured to:

select one of the local count cache register and the global count cache register to provide the selected predicted target based on the selector associated with one of the first and second predicted targets.

15. The processor of claim 13 , wherein the processor core is further configured to:

increment a first count, associated with the first predicted target in the local count cache, in response to the first predicted target being a correct target following execution of the indirect branch instruction; and

decrement the first count in response to the first predicted target not being the correct target.

16. The processor of claim 13 , wherein the processor core is further configured to:

increment a second count, associated with the second predicted target in the global count cache, in response to the second predicted target being a correct target following execution of the indirect branch instruction; and

decrement the second count in response to the second predicted target not being the correct target.

17. The processor of claim 15 , wherein the processor core is further configured to:

maintain the entry associated with the second predicted target in the global count cache when the local count cache is selected and the first count is above a predetermined value; and

replace the entry in the global count cache when the local count cache is selected and the first count is below the predetermined value.

18. A data processing system, comprising:

the processor of claim 13 ; and

a data storage subsystem coupled to the processor.

19. The processor of claim 13 , wherein the processor core is further configured to:

exclusive OR the instruction fetch address with the global history vector to provide an index; and

select the entry in the global count cache based on the index.

20. The processor of claim 12 , wherein at least some of the first and second predicted targets are the same.