Transition metal oxide bilayers
View Patent ↗Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen.
1. A nonvolatile memory element comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode;
a third layer comprising Me 1 w Me 2 x Si y O z between the first layer and the second layer; and
a fourth layer comprising Me 1 a Me 2 b Si c O d between the first layer and the second layer;
wherein Me 1 and Me 2 are metals;
wherein w≧0, x≧0, y≧0, z>0, a≧0, b≧0, c≧0, and d>0;
wherein at least one of w, x, or y>0;
wherein at least one of a, b, or c>0;
wherein one of the third layer or the fourth layer has a linear resistance and a substoichiometric composition; and
wherein another one of the third layer or the fourth layer has a bistable resistance and a near-stoichiometric composition.
2. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises nitrogen.
3. The nonvolatile memory element of claim 1 , wherein the third layer and the fourth layer comprise nitrogen.
4. The nonvolatile memory element of claim 1 , wherein the one of the third layer or the fourth layer having the sub-stoichiometric composition comprises Ta 2 O 5-δ , and wherein δ is less than 0.0005.
5. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises tantalum oxide.
6. The nonvolatile memory element of claim 1 , wherein the third layer and the fourth layer comprise tantalum oxide.
7. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises tantalum oxynitride.
8. The nonvolatile memory element of claim 1 , wherein the third layer and the fourth layer comprise tantalum oxynitride.
9. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises one of tantalum, niobium, hafnium, yttrium, zirconium, lanthanum, vanadium, titanium, tungsten, nickel, aluminum, silicon, or combinations thereof.
10. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises one of aluminum oxide, aluminum oxynitride, silicon oxide, or silicon oxynitride.
11. The nonvolatile memory element of claim 1 , wherein the first layer comprises doped polysilicon; and wherein the one of the third layer and the fourth layer having the bistable resistance is adjacent to the first layer.
12. The nonvolatile memory element of claim 11 , wherein the second layer comprises titanium nitride; and wherein the one of the third layer and the fourth layer having the linear resistance is adjacent to the second layer.
13. The nonvolatile memory element of claim 1 , wherein the second layer comprises titanium nitride; and wherein the one of the third layer and the fourth layer having the linear resistance is adjacent to the second layer.
14. The nonvolatile memory element of claim 1 , wherein a combined thickness of the third layer and the fourth layer is between about 20 Å and about 100 Å.
15. The nonvolatile memory element of claim 1 , wherein the one of the third layer and the fourth layer having the bistable resistance has a thickness of between about 25% and about 75% of a combined thickness of the third layer and the fourth layer.
16. The nonvolatile memory element of claim 1 , wherein the one of the third layer and the fourth layer having the bistable resistance has a thickness of about 25% of a combined thickness of the third layer and the fourth layer.
17. The nonvolatile memory element of claim 1 , wherein w and x are greater than zero.
18. The nonvolatile memory element of claim 1 , wherein a and b are greater than zero.
19. A nonvolatile memory element comprising:
a first layer operable as a first electrode;
a second layer operable as a second electrode;
a third layer having a bistable resistance; and
a fourth layer having a linear resistance;
wherein the first layer comprises titanium nitride;
wherein the second layer comprises doped polysilicon;
wherein the third layer comprises near-stoichiometric tantalum oxide;
wherein the fourth layer comprises sub-stoichiometric tantalum oxide;
wherein the third layer is disposed between the first layer and the fourth layer; and
wherein the fourth layer is disposed between the third layer and the second layer.
20. A method of forming a nonvolatile memory element, the method comprising:
forming a first layer on a substrate; and
forming a second layer on the first layer;
wherein the first layer comprises Me 1 w Me 2 x Si y O z ;
wherein the second layer comprises Me 1 a Me 2 b Si c O d ;
wherein Me 1 and Me 2 are metals;
wherein w≧0, x≧0, y≧0, z>0, a≧0, b≧0, c≧0, and d>0;
wherein at least one of w, x, or y is greater than zero;
wherein at least one of a, b, and c is greater than zero;
wherein one of the first layer or the second layer has a linear resistance and a substoichiometric composition; and
wherein another one of the first layer and the second layer has a bistable resistance and a near-stoichiometric composition.