High capacity low cost multi-stacked cross-line magnetic memory
View Patent ↗One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
1. A method of manufacturing a diode-addressable current-induced magnetization switching (CIMS) memory element comprising:
Forming decoder transistors on a CMOS substrate;
Depositing a first metal layer on top of the decoder transistors;
Depositing a magnetic tunnel junction (MTJ) on the first metal layer, etching, depositing a second metal layer on top of the first metal layer and depositing silicon oxide on the etched second metal layer;
Depositing a third metal layer on top of the silicon oxide to form an erase line;
Depositing a magnetic shielding layer to form a first stack;
forming a second stack on top of the first stack.
2. The method of manufacturing, a recited in claim 1 , wherein the depositing the magnetic shielding layer step including depositing a second silicon oxide on top of the magnetic shielding layer.
3. The method of manufacturing, a recited in claim 2 , wherein the depositing the magnetic shielding layer step including chemical mechanical polishing prior to forming the second stack.
4. The method of manufacturing, a recited in claim 1 , wherein the forming a second stack step including depositing a fourth metal and forming a diode on top of the fourth metal.
5. The method of manufacturing, a recited in claim 4 , wherein the forming a second stack step including forming a diode on top of the fourth metal and etching.
6. The method of manufacturing, a recited in claim 5 , wherein the forming a second stack step including depositing a fifth metal layer on top of the etched diode.
7. The method of manufacturing, a recited in claim 6 , further including depositing a field erase-line on top of the fifth metal.
8. The method of manufacturing, a recited in claim 7 , further including depositing a second magnetic shielding layer on top of the field erase-line.
9. The method of manufacturing, as recited in claim 8 , further including depositing a third silicon oxide layer and chemical mechanical polishing.