IP Library Granted Patent US 8,891,326
Granted Patent B1
US 8,891,326 · App. 14/024,580 · Granted Nov 18, 2014

Method of sensing data in magnetic random access memory with overlap of high and low resistance distributions

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Quick Facts
Patent No.
US 8,891,326
App. No.
14/024,580
Granted
Nov 18, 2014
Kind
B1
Abstract

A method of writing to a magneto tunnel junction (MTJ) includes writing data to the MTJ, reading the written data using a first reference MTJ and reading the written data using a second reference MTJ. Based on the reading steps and the result of the comparing step, setting a select bit to select the proper reference for future reads.

Claims (20)

1. A method of writing to a magneto tunnel junction (MTJ) comprising:

writing data to the MTJ, the MTJ configured to store a bit of information representing two logical states;

after the writing data step, first reading the written data using a first reference MTJ;

after the writing data step, second reading the written data written using a second reference MTJ;

first comparing the data read during the first reading step to a first predetermined value;

second comparing the data read during the second reading step to a second predetermined value; and

based on the result of the first and the second comparing steps, setting a select bit, the select bit being indicative of using the first reference MTJ or the second reference MTJ for subsequent writes to the MTJ.

2. The method of writing of claim 1 , wherein the first reading step occurs at substantially the same time as the second reading step.

3. The method of writing of claim 1 , wherein the first and second predetermined values are determined prior to the writing step.

4. The method of writing of claim 1 , further including saving the select bit for subsequent write operations.

5. The method of writing of claim 1 , wherein the first comparing step is performed after the first reading step and the second comparing step is performed after the second reading step.

6. The method of writing of claim 1 , wherein the setting step includes setting more than one select bit.

7. The method of writing of claim 1 , wherein the first comparing step includes checking for logical state of all ‘1’s and based on the result of the first comparing step, setting the select bit to logical state ‘1’ or logical state ‘0’.

8. The method of writing of claim 1 , wherein the second comparing step includes checking for logical state of all ‘1’s and based on the result of the second comparing step, setting the select bit to logical state ‘1’ or logical state ‘0’.

9. The method of writing of claim 1 , wherein the first comparing step includes checking for logical state of all ‘0’s and based on the result of the first comparing step, setting the select bit to logical state ‘1’ or logical state ‘0’.

10. The method of writing of claim 1 , wherein the second comparing step includes checking for logical state of all ‘0’s and based on the result of the second comparing step, setting the select bit to logical state ‘1’ or logical state ‘0’.

11. The method of writing of claim 1 , wherein the select bit is indicative of the state of the written data, after the written data has been read during the first and second reading steps.

12. The method of writing of claim 1 , wherein the select bit is indicative of the state of the written data after the written data has been read during the first and second reading steps being corrupt or not.

13. The method of writing of claim 1 , wherein the more than one bit is indicative of the state of data written to the MTJ after the written data has been read during the first and second reading steps, as being unreliable, reliable using either the first or the second reference MTJ for reading, reliable only when using one of the first or second reference MTJs for reading.

14. The method of writing of claim 1 , wherein the MTJ is a multi-level MTJ configured to store more than one two logical states.

Assignments (7)
SECURITY INTEREST Recorded Mar 18, 2022
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 059436/0203 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057213/0050 →
SECURITY INTEREST Recorded Apr 19, 2021
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 057217/0674 →
SECURITY INTEREST Recorded Jul 8, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: SILICON VALLEY BANK
Reel/Frame 053156/0223 →
SECURITY INTEREST Recorded Feb 13, 2020
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 051930/0396 →
SECURITY INTEREST Recorded Apr 18, 2017
From: AVALANCHE TECHNOLOGY, INC.
To: STRUCTURED ALPHA LP
Reel/Frame 042273/0813 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: ABEDIFARD, EBRAHIM; MOZAFFARI, MAHMOOD; ESTAKHRI, PETRO; KESHTBOD, PARVIZ
To: AVALANCHE TECHNOLOGY, INC.
Reel/Frame 031187/0642 →