Stacked nanowire device with variable number of nanowire channels

1. A method of forming a semiconductor structure comprising:

forming a stack of layers on a top surface of a substrate, the stack of layers consisting of alternating layers of a semiconductor material and a sacrificial semiconductor material, one on top of the other, wherein a bottommost layer of the stack of layers is a top semiconductor layer of the substrate;

patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels comprising the semiconductor material, and the plurality of sacrificial spacers comprising the sacrificial semiconductor material;

forming a shallow trench isolation region between the plurality of material stacks, wherein a topmost surface of the shallow trench isolation region is flush with, or located beneath, a topmost surface of the top semiconductor layer of the substrate; and

removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from an adjacent material stack.

2. The method of claim 1 , wherein the semiconductor substrate is a semiconductor-on-insulator and the bottommost layer of the stack of layers is located on a buried insulating layer.

3. The method of claim 1 , wherein forming the stack of layers on the top surface of the substrate comprises:

epitaxially growing the alternating layers of the semiconductor material and the sacrificial semiconductor material, the epitaxial growth process is performed at a temperature of below 800° C. and at a pressure below 100 torr.

4. The method of claim 1 , wherein removing the at least one of the plurality of nanowire channels from the at least one of the plurality of material stacks without removing one or more of the plurality of nanowire channels from the adjacent material stack comprises:

protecting some of the plurality of material stacks with a mask;

removing one or more of the topmost nanowire channels from the plurality of material stacks not protected by the mask; and

removing one or more of the topmost sacrificial spacers from the plurality of material stacks not protected by the mask.

5. The method of claim 1 , further comprising:

forming a gate electrode over and all around a central portion of each of the plurality of nanowire channels.

6. The method of claim 1 , further comprising:

forming a source region and a drain region each self-aligned to a gate electrode, the gate electrode formed over and all around a central portion of each of the plurality of nanowire channels.

7. A method of forming a semiconductor structure comprising:

forming a stack of layers on a top surface of a substrate, the stack of layers consisting of alternating layers of a semiconductor material and a sacrificial semiconductor material, one on top of the other, wherein a bottommost layer of the stack of layers is a top semiconductor layer of the substrate;

patterning a plurality of material stacks from the stack of layers, each material stack including an alternating stack of a plurality of nanowire channels and a plurality of sacrificial spacers, the plurality of nanowire channels comprising the semiconductor material, and the plurality of sacrificial spacers comprising the sacrificial semiconductor material;

forming a shallow trench isolation region between the plurality of material stacks, wherein a topmost surface of the shallow trench isolation region is flush with, or located beneath, a topmost surface of the top semiconductor layer of the substrate;

removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one of the plurality of nanowire channels from an adjacent material stack;

forming a dummy gate directly on a central portion of each of the plurality of material stacks;

forming a pair of sidewall spacers abutting opposite sides of the dummy gate;

removing a portion of the plurality of sacrificial spacers not covered by the dummy gate to create one or more openings between the plurality of nanowire channels;

depositing a dielectric material in the one or more openings between the plurality of nanowire channels;

forming a source region and a drain region each self-aligned to opposite sidewall spacers, the source region and the drain region being in direct contact with opposite end segments of the plurality of nanowire channels;

removing the dummy gate to form a trench over the central portion of the plurality of material stacks;

removing the plurality of sacrificial spacers exposed in the trench selective to the plurality of nanowire channels; and

forming a gate electrode within the trench and all around the plurality of nanowire channels.

8. The method of claim 7 , wherein the semiconductor substrate is a semiconductor-on-insulator and the bottommost layer of the stack of layers is located on a buried insulating layer.

9. The method of claim 7 , wherein forming the stack of layers on the top surface of the substrate comprises:

epitaxially growing the alternating layers of the semiconductor material and the sacrificial semiconductor material, the epitaxial growth process is performed at a temperature of below 800° C. and at a pressure below 100 torr.

10. The method of claim 7 , wherein removing the portion of the plurality of sacrificial spacers not covered by the dummy gate to create the one or more openings between the plurality of nanowire channels comprises:

using an etchant that exploits the lower oxidation potential of the layers of sacrificial semiconductor material compared to the layers of semiconductor material.

11. The method of claim 7 , wherein removing the portion of the plurality of sacrificial spacers not covered by the dummy gate to create the one or more openings between the plurality of nanowire channels comprises:

using a plasma etching process.

12. The method of claim 7 , wherein removing the portion of the plurality of sacrificial spacers not covered by the dummy gate to create the one or more openings between the plurality of nanowire channels comprises:

using a wet or dry oxidation process performed at a temperature of less than 750° C.

13. The method of claim 7 , wherein removing at least one of the plurality of nanowire channels from at least one of the plurality of material stacks without removing one of the plurality of nanowire channels from the adjacent material stack comprises:

protecting some of the plurality of material stacks with a mask;

removing one or more of the topmost nanowire channels from the plurality of material stacks not protected by the mask; and

removing one or more of the topmost sacrificial spacers from the plurality of material stacks not protected by the mask.