Granted Patent B2

US 8,980,649 · App. 14/028,216 · Granted Mar 17, 2015

Abstract

Claims (28)

1. A method of manufacturing a magnetic random access memory (MRAM) cell comprising

performing a front end on-line (FEOL) stage, in a first facility, to make logic and non-magnetic portions of a memory cell being manufactured including the steps of,

forming an intermediate interlayer dielectric (ILD) layer in the first facility;

forming intermediate metal pillars embedded in the intermediate ILD layer in the first facility; and

depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars to seal the intermediate ILD layer and the intermediate metal pillars, wherein after the depositing step, a FEOL stage structure is formed;

performing magnetic fabrication stage, in a second facility separate and apart from the first facility, to make a magnetic material portion of the memory cell being manufactured; and

performing back end on-line (BEOL) stage, in the second facility to make metal and contacts of the memory cell being manufactured.

2. A method of manufacturing, as recited in claim 1 , wherein the FEOL stage further includes the steps of: forming logic on top of a wafer, onto which memory cells are to be formed;

forming a first ILD layer on top of the logic; and

forming a plurality of first metal pillars dispersed in the first ILD layer.

3. A method of constructing a MRAM memory cell, as recited in claim 2 , where the first metal pillars are made of tungsten.

4. A method of constructing a MRAM memory cell, as recited in claim 2 , where the intermediate ILD layer is formed using a damascene process comprising:

forming a intermediate ILD layer on top of the first ILD layer and first metal pillars;

depositing photo resist on top of the intermediate ILD layer in a manner which covers substantially all of the ILD layer except the portion above the first metal pillars;

etching the intermediate ILD layer until the first metal pillars are exposed;

depositing a metal layer until the metal contacts the exposed, first metal pillars;

planerizing the metal leaving in place the second metal pillars.

5. A method of constructing a MRAM memory cell, as recited in claim 4 , where the second metal pillars are formed from copper.

6. A method of constructing a MRAM memory cell, as recited in claim 1 , where the intermediate ILD layer etching is done using reactive ion etching (RIE).

7. A method of constructing a MRAM memory cell, as recited in claim 2 , where the intermediate ILD layer is formed using a non-damascene process comprising:

depositing a metal layer on top of the first ILD layer and first metal pillars;

depositing photo-resist pillars on top of the metal layer in a pattern substantially above the first metal pillars;

etching the metal layer until the second metal pillars remain;

depositing an ILD layer covering the entire wafer including the second metal pillars;

planerizing the ILD layer until the tops of the second metal pillars are exposed.

8. A method of constructing a MRAM memory cell, as recited in claim 2 , where the second metal pillars are formed of copper.

9. A method of constructing a MRAM memory cell, as recited in claim 2 , where the metal layer etching is done using reactive ion etching (RIE).

10. A method of constructing a MRAM memory cell, as recited in claim 2 , where the first conductive metal cap is made of Tantalum, Tantalum Nitride, Titanium, Titanium Nitride, Chromium, Tungsten, Niobium or alloys containing one or more of these elements.

Assignments (6)