Access transistor with a buried gate
View Patent ↗A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.
1. A semiconductor device comprising:
a semiconductor substrate having a mesa protruded therefrom;
a drain and a source having a first type conductivity formed in a top portion and a bottom portion of said mesa, respectively;
a channel region having a second type conductivity opposite to said first type formed between said source and said drain in said mesa; and
a pair of gates formed on opposite sides of said channel region with a gate oxide interposed therebetween,
wherein a pair of conductive channels are formed on opposite surfaces of said channel region adjacent to said pair of gates to allow substantially vertical flow of electric current between said source and said drain upon application of an appropriate voltage to said pair of gates.
2. The semiconductor device according to claim 1 , wherein said first and second type conductivities are n-type and p-type, respectively.
3. The semiconductor device according to claim 1 , wherein said first and second type conductivities are p-type and n-type, respectively.
4. The semiconductor device according to claim 1 , wherein said semiconductor substrate is made of silicon.
5. The semiconductor device according to claim 1 , wherein said pair of gates are made of a doped polysilicon.
6. The semiconductor device according to claim 1 , wherein said gate oxide is made of silicon oxide.
7. The semiconductor device according to claim 1 further comprising a word line coupled to said pair of gates.
8. The semiconductor device according to claim 1 further comprising a memory element disposed on top of said drain.
9. The semiconductor device according to claim 8 , wherein said memory element comprises a layer of phase shift memory alloy.
10. The semiconductor device according to claim 8 , wherein said memory element includes a magnetic tunnel junction (MTJ) comprising two ferromagnetic layers with a non-magnetic tunnel barrier layer interposed therebetween.
11. The semiconductor device according to claim 8 further comprising a bit line disposed on top of said memory element.
12. A semiconductor device comprising:
a plurality of memory cells, each of said plurality of memory cells including an access transistor and a memory element formed thereon, said access transistor comprising:
a semiconductor substrate having a mesa protruded therefrom;
a drain and a source having a first type conductivity formed in a top portion and a bottom portion of said mesa, respectively;
a channel region having a second type conductivity opposite to said first type formed between said source and said drain in said mesa; and
a pair of gates formed on opposite sides of said channel region with a gate oxide interposed therebetween,
wherein a pair of conductive channels are formed on opposite surfaces of said channel region adjacent to said pair of gates to allow substantially vertical flow of electric current between said source and said drain upon application of an appropriate voltage to said pair of gates;
a plurality of parallel bit lines with each bit line coupled to a respective row of said memory elements therebeneath in a first direction; and
a plurality of parallel word lines with each word line coupled to a respectively row of said gates in a second direction perpendicular to said first direction.
13. The semiconductor device according to claim 12 , wherein said first and second type conductivities are n-type and p-type, respectively.
14. The semiconductor device according to claim 12 , wherein said first and second type conductivities are p-type and n-type, respectively.
15. The semiconductor device according to claim 12 , wherein said semiconductor substrate is made of silicon.
16. The semiconductor device according to claim 12 , wherein said pair of gates are made of a doped polysilicon.
17. The semiconductor device according to claim 12 , wherein said gate oxide is made of silicon oxide.
18. The semiconductor device according to claim 12 , wherein said memory element comprises a layer of phase shift memory alloy.
19. The semiconductor device according to claim 12 , wherein said memory element includes a magnetic tunnel junction (MTJ) comprising two ferromagnetic layers with a non-magnetic tunnel barrier layer interposed therebetween.