Method and system for operating gallium nitride electronics
View Patent ↗An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.
1. An electronic circuit comprising:
a driver comprising:
a bias voltage generator configured to receive a voltage input and generate a biased voltage output based on the voltage input;
a supplementary transistor having a gate, a drain, and a source, wherein:
the gate of the supplementary transistor is coupled to the biased voltage output of the bias voltage generator; and
the source of the supplementary transistor provides a current to the bias voltage generator; and
an output driver configured to:
receive the biased voltage output from the bias voltage generator and the voltage input;
receive the voltage input; and
output a drive voltage; and
a main transistor having a gate, a drain, and a source, wherein:
the gate of the main transistor is coupled to the drive voltage; and
the drain of the main transistor is coupled to the drain of the supplementary transistor.
2. The electronic circuit of claim 1 , wherein the supplementary transistor is a GaN transistor, such that:
the drain of the supplementary transistor comprises a GaN substrate and a drain contact;
the source of the supplementary transistor is separated from the GaN substrate by a drift region and comprises a source contact;
the drift region of the supplementary transistor comprises a first GaN epitaxial layer coupled to the GaN substrate; and
the gate of the supplementary transistor comprises a second GaN epitaxial layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased voltage output of the bias voltage generator.
3. The electronic circuit of claim 1 , the driver further comprising a current monitor configured to detect a current from the drain to the source of the supplementary transistor and output a regulated current, wherein the output driver further is configured to receive the regulated current from the current monitor.
4. The electronic circuit of claim 1 wherein the current monitor regulates the current from the drain of the supplementary transistor to the source of the supplementary transistor.
5. The electronic circuit of claim 1 wherein the supplementary transistor and the main transistor are junction gate field-effect transistors (JFET).
6. The electronic circuit of claim 1 wherein the output driver is a voltage converter.
7. The electronic circuit of claim 6 wherein the driver is driven by a voltage at the drain of the main transistor.
8. The electronic circuit of claim 1 wherein the driver and the main transistor are co-packaged in a same package.
9. The electronic circuit of claim 8 wherein the driver and the main transistor are on different dies.
10. The electronic circuit of claim 9 wherein the main transistor is a GaN JFET.
11. A method of operating a GaN JFET, the method comprising:
receiving, at a GaN JFET driver, an input voltage;
generating a biased voltage output based on the input voltage;
monitoring a current of a supplementary transistor to provide a current value;
receiving, at an output driver, the biased voltage output, the current value, and the input voltage;
generating an output drive voltage based on the biased voltage output, the current value, and the input voltage; and
providing, to the GaN JFET, the output drive voltage.
12. The method of claim 11 wherein the input voltage comprises a pulsed input voltage.
13. The method of claim 11 wherein the current value is based on the current from the drain to the source of the supplementary transistor.
14. The method of claim 11 wherein the output drive voltage is characterized by a lower amplitude than the input voltage.
15. The method of claim 11 wherein the supplementary transistor comprises a GaN FET.
16. The method of claim 11 wherein the output drive voltage is generated by a voltage converter.
17. The method of claim 16 wherein the voltage converter is driven by a voltage at a drain of the main transistor.
18. The method of claim 11 further comprising packaging the driver and the main transistor in a same package.
19. The method of claim 18 wherein the driver and the main transistor are on different dies.