Granted Patent B2

US 9,123,799 · App. 14/077,039 · Granted Sep 1, 2015

Abstract

Claims (31)

1. A method for fabricating a lateral-channel/lateral-drift GaN field-effect transistor (FET), the method comprising:

providing a substrate;

providing a first GaN layer coupled to the substrate, wherein the first GaN layer has a first conductivity type;

forming a second GaN layer coupled to the first GaN layer, wherein the second GaN layer has a second conductivity type;

removing a portion of the second GaN layer to expose a portion of the first GaN layer;

forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer, wherein the third GaN layer has a third conductivity type;

removing a portion of the third GaN layer to expose a portion of the second GaN layer;

forming a source structure coupled to the third GaN layer, wherein a first portion of the third GaN layer is disposed between the source structure and the second GaN layer;

forming a drain structure coupled to the third GaN layer; and

forming a gate structure coupled to the third GaN layer, wherein a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.

2. The method of claim 1 further comprising forming a contact coupled to the exposed portion of the second GaN layer.

3. The method of claim 1 further comprising removing portions of the second GaN layer to form a plurality of sections that are progressively thinner as a distance from the second GaN layer to the gate structure increases.

4. The method of claim 1 wherein forming the gate structure comprises forming the gate structure with metal.

5. The method of claim 1 wherein forming the gate structure comprises forming the gate structure incorporating GaN of the second conductivity type.

6. The method of claim 1 further comprising removing a second portion of the second GaN layer, wherein the first portion of the third GaN layer is thinner than the second portion of the third GaN layer.

7. The method of claim 1 wherein the third GaN layer comprises n-type GaN.

8. The method of claim 1 wherein the second GaN layer comprises p-type GaN.

9. The method of claim 1 wherein at least one of the source structure, the drain structure, or the gate structure comprises a metal.

10. The method of claim 1 wherein at least one of the source structure, the drain structure, or the gate structure comprises a metal and a semiconductor material.

11. A method for fabricating a lateral-channel/vertical-drift GaN field-effect transistor (FET), the method comprising:

providing a substrate;

providing a first GaN layer coupled to the substrate, therein the first GaN layer has a first conductivity type;

forming a second GaN layer coupled to the first GaN layer, wherein the second GaN layer has a second conductivity type;

removing a portion of the second GaN layer to expose a portion of the first GaN layer;

forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer, wherein the third GaN layer has a third conductivity type;

removing a portion of the third GaN layer to expose a portion of the second GaN layer;

forming a source structure coupled to the third GaN layer, wherein a first portion of the third GaN layer is disposed between the source structure and the second GaN layer;

forming a drain structure coupled to the substrate; and

forming a gate structure coupled to the third GaN layer, wherein a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.

12. The method of claim 11 further comprising removing portions of the second GaN layer to form a plurality of sections that are progressively thinner as a distance from the second GaN layer to the gate structure increases.

13. The method of claim 11 the first portion of the third GaN layer is thinner than the second portion of the third GaN layer.

Assignments (12)