Wire bondable surface for microelectronic devices
View Patent ↗The present invention concerns thin diffusion barriers in metal and metal alloy layer sequences of contact area/barrier layer/first bonding layer type for metal wire bonding applications. The diffusion barrier is selected from Co-M-P. Co-M-B and Co-M-B—P alloys wherein M is selected from Mn, Zr, Re, Mo, Ta and W having a thickness in the range 0.03 to 0.3 μm. The first bonding layer is selected from palladium and palladium alloys.
1. A semiconducting substrate comprising at least one metal layer sequence to produce a metal wire bondable surface wherein said layer sequence consists in this order of
(i) a plurality of adjacent contact areas, wherein the adjacent contact areas are positioned within 5 μm of each other,
(ii) a barrier layer selected from the group consisting of Co—Mo—P, Co—W—P, Co—Mo—B, Co—W—B, Co—Mo—B—P or Co—W—B—P alloys,
wherein the thickness of said barrier layer ranges from 0.05 to 0.15 μm and
(iii) pure palladium as a first bonding layer having a thickness in the range of 0.05 to 0.3 μm,
wherein the stack further comprises a second bonding layer on top of the first bonding layer, the second bonding layer is selected from the group consisting of gold and gold alloys, and the thickness of the second bonding layer ranges from 0.02 to 0.1 μm,
wherein a total thickness of said layer sequence is sufficient to provide both reduced risk of bridging and sufficient mechanical stability to prevent damage to the substrate during metal wire bonding operations.
2. The semiconducting substrate according to claim 1 wherein the thickness of the first bonding layer ranges from 0.1 to 0.2 μm.