Method and device for an integrated trench capacitor
A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.
1. A method comprising:
forming a polymer block on a front side of an interposer wafer;
patterning and etching the polymer block to form one or more trenches;
conformally forming a first metal layer in the one or more trenches, upper and side surfaces of the polymer block, an exposed surface of the interposer wafer, and a connection pad formed on the interposer wafer;
removing the first metal layer from the exposed surface of the interposer wafer, the connection pad, and the side surfaces of the polymer block; and
forming a capacitor on an upper surface of the polymer block and in the one or more trenches.
2. The method according to claim 1 , further comprising pulling the first metal layer back from outer edges of the polymer block.
3. The method according to claim 1 , further comprising:
conformally forming a dielectric layer on the exposed surface of the interposer wafer, the connection pad, the side surfaces of the polymer block, and the first metal layer; and
removing the dielectric layer from the exposed surface of the interposer wafer and the connection pad.
4. The method according to claim 3 , further comprising:
forming a second metal layer on the exposed surface of the interposer wafer, the connection pad, and the dielectric layer; and
removing the second metal layer from the exposed surface of the interposer wafer.
5. The method according to claim 1 , further comprising:
forming a polymer layer on the front side of the interposer wafer;
patterning and etching the polymer layer to form the polymer block at one or more connection pads on the interposer wafer.
6. The method according to claim 1 , wherein the one or more trenches comprise one or more holes or one or more troughs in the polymer block.
7. The method according to claim 1 , wherein the one or more trenches have an aspect ratio of 1:20 to 1:25.
8. The method according to claim 1 , wherein the polymer layer is formed to a thickness of up to 100 micrometers (μm).
9. A method comprising:
forming a polymer layer on a front side of an interposer wafer;
patterning and etching the polymer layer to form a polymer block at one or more connection pads on the interposer wafer,
patterning and etching the polymer block to form one or more trenches;
conformally forming a first metal layer in the one or more trenches, upper and side surfaces of the polymer block, an exposed surface of the interposer wafer, and one of the one or more connection pads;
removing the first metal layer from the exposed surface of the interposer wafer, the one of the one or more connection pads, and the side surfaces of the polymer block;
pulling the first metal layer back from outer edges of the polymer block;
conformally forming a dielectric layer on the exposed surface of the interposer wafer, the one of the one or more connection pads, the side surfaces of the polymer block, and the first metal layer;
removing the dielectric layer from the exposed surface of the interposer wafer and the one of the one or more connection pads;
forming a second metal layer on the exposed surface of the interposer wafer, the one of the one or more connection pads, and the dielectric layer; and
removing the second metal layer from the exposed surface of the interposer wafer.
10. The method according to claim 9 , wherein the one or more trenches comprise one or more holes or one or more troughs in the polymer block.
11. The method according to claim 9 , wherein the one or more trenches have an aspect ratio of 1:20 to 1:25.