IP Library Granted Patent US 9,202,742
Granted Patent B1
US 9,202,742 · App. 14/156,271 · Granted Dec 1, 2015

Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof

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Quick Facts
Patent No.
US 9,202,742
App. No.
14/156,271
Granted
Dec 1, 2015
Kind
B1
Abstract

An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate; a device attached on a top surface of the substrate; a mold encapsulating the device, the mold having a through via and a recessed pattern characterized by being formed in a single process; and a conductive via in the through via and a conductive pattern in the recessed pattern characterized by being formed in another single process.

Claims (39)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching a device on a top surface of the substrate;

encapsulating the device in a mold;

forming through vias and recessed patterns in a top surface of the mold in a single process with the through vias open to the substrate; and

forming a one-piece multi-depth structure having conductive vias in the through vias and conductive patterns in the recessed patterns in a single filling process, the conductive patterns having a variety of shapes, depths, and sizes, the conductive patterns being for connections among the conductive vias, the one-piece multi-depth structure has no internal metal boundaries characteristic of the single filling process.

2. The method as claimed in claim 1 wherein forming the through vias and the recessed patterns includes using laser ablation.

3. The method as claimed in claim 1 wherein:

forming the through vias and the recessed patterns includes drilling the through vias and drilling the recessed patterns at the top surface of the mold; and

forming the conductive vias and the conductive patterns includes patterning the conductive vias and the conductive patterns such that the conductive patterns are for connections among the conductive vias.

4. The method as claimed in claim 1 further comprising mounting a top package over the conductive vias.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching a device on a top surface of the substrate;

encapsulating the device in a mold;

forming an external connector at an external surface of the substrate;

forming through vias and recessed patterns in a top surface of the mold in a single process with the through vias open to the substrate; and

forming a one-piece multi-depth structure having conductive vias in the through vias and conductive patterns in the recessed patterns in a single filling process, the conductive vias and the conductive patterns have a variety of shapes, depths, and sizes, and the conductive patterns are for connections among the conductive vias, the one-piece multi-depth structure has no internal metal boundaries characteristic of the single filling process.

6. The method as claimed in claim 5 wherein forming the through vias and the recessed patterns includes using laser ablation or dry film lamination.

7. The method as claimed in claim 5 wherein:

forming the through vias and the recessed patterns includes drilling the through vias with expositions of the top surface, and drilling the recessed patterns at the top surface of the mold before reaching the top surface of the substrate or the device; and

forming the conductive vias and the conductive patterns includes patterning the conductive vias and the conductive patterns such that the conductive patterns are for connections among the conductive vias.

8. The method as claimed in claim 5 further comprising mounting a top package having an additional device over the conductive vias.

9. An integrated circuit packaging system comprising:

a substrate;

a device attached on a top surface of the substrate;

a mold encapsulating the device, the mold having through vias and recessed patterns characterized by being formed in a single process; and

a one-piece multi-depth structure having conductive vias in the through vias and conductive patterns in the recessed patterns, the one-piece multi-depth structure has no internal metal boundaries characterized by being formed in a single filling process, the conductive vias and the conductive patterns have a variety of shapes, depths and sizes, and the conductive patterns are for connections among the conductive vias.

10. The system as claimed in claim 9 wherein the through vias and the recessed patterns include physical marks characteristic of being formed using laser ablation.

11. The system as claimed in claim 9 wherein:

the through vias and the recessed patterns include the through vias and the recessed patterns having drilled marks at a top surface of the mold; and

the conductive vias and the conductive patterns include the conductive vias and the conductive patterns for connections among the conductive vias and the conductive patterns.

12. The system as claimed in claim 9 further comprising a top package over the conductive vias.

13. The system as claimed in claim 9 further comprising an external connector at an external surface of the substrate.

14. The system as claimed in claim 13 wherein the through vias and the recessed patterns include physical marks characteristic of being formed using laser ablation or dry film lamination.

15. The system as claimed in claim 13 wherein:

the through vias and the recessed patterns include the through vias with expositions of the top surface, the through vias and the recessed patterns having drilled marks at a top surface of the mold; and the conductive patterns are for connections among the conductive vias.

16. The system as claimed in claim 13 wherein the conductive vias and the conductive patterns include a variety of shapes, depths, and sizes of conductive vias.

17. The system as claimed in claim 13 further comprising a top package having an additional device over the conductive vias.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CHANGE OF NAME Recorded Jul 22, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039428/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: KIM, WOO JIN; KIM, SUN JAE; AHN, CHUNG LYUL; KANG, HYEON YI
To: STATS CHIPPAC LTD.
Reel/Frame 031978/0900 →