Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
View Patent ↗A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.
1. A method of making a semiconductor device, comprising:
providing a substrate including a first conductive layer;
disposing a semiconductor die including a second conductive layer over the substrate;
forming an interconnect structure comprising a fusible portion and a non-fusible portion; and
reflowing the interconnect structure self-confined by a surface tension over the first conductive layer or second conductive layer.
2. The method of claim 1 , further including forming an insulating layer over the substrate around the first conductive layer.
3. The method of claim 1 , further including depositing an underfill material between the semiconductor die and the substrate.
4. The method of claim 1 , further including forming the interconnect structure without a solder mask.
5. The method of claim 1 , further including forming a flux solution over the interconnect structure.
6. A method of making a semiconductor device, comprising:
providing a first substrate including a first conductive layer; and
reflowing a composite interconnect structure self-confined over the first conductive layer.
7. The method of claim 6 , further including disposing a second substrate including a second conductive layer over the composite interconnect structure.
8. The method of claim 7 , further including selecting a volume of the composite interconnect structure in relation to an area of the first conductive layer and second conductive layer to maintain self-confinement of the composite interconnect structure by a surface tension of the composite interconnect structure.
9. The method of claim 7 , further including depositing an underfill material between the first substrate and second substrate.
10. The method of claim 6 , further including forming an insulating layer over the first substrate around the first conductive layer.
11. The method of claim 6 , further including forming a flux solution over the composite interconnect structure.
12. The method of claim 6 , further including forming the composite interconnect structure without a solder mask.
13. A semiconductor device, comprising:
a substrate including a first conductive layer;
a semiconductor die including a second conductive layer disposed over the substrate; and
a composite interconnect structure reflowed and self-confined over the first conductive layer or second conductive layer.
14. The semiconductor device of claim 13 , wherein the first conductive layer includes a trace or a bump pad.
15. The semiconductor device of claim 13 , further including an underfill material deposited between the semiconductor die and substrate.
16. The semiconductor device of claim 13 , wherein a width of the first or second conductive layer is less than a width of the composite interconnect structure.
17. The semiconductor device of claim 13 , wherein an escape pitch of the first conductive layer is given D/2+PLT+W/2, wherein D is a base diameter of the composite interconnect structure, PLT is die placement tolerance, and W is a width of the first conductive layer.
18. The semiconductor device of claim 13 , wherein a height of the composite interconnect structure is less than a diameter of the composite interconnect structure.
19. The semiconductor device of claim 13 , wherein the composite interconnect structure includes copper.
20. A semiconductor device, comprising:
a first substrate including a first conductive layer; and
an interconnect structure bonded to and self-confined over the first conductive layer, wherein the interconnect structure includes a non-fusible portion and fusible portion.
21. The semiconductor device of claim 20 , further including a second substrate including a second conductive layer disposed over the interconnect structure.
22. The semiconductor device of claim 20 , wherein the first conductive layer includes a trace or a bump pad.
23. The semiconductor device of claim 20 , wherein a width of the first conductive layer is less than a width of the interconnect structure.
24. The semiconductor device of claim 20 , further including an insulating layer formed over an area of the first conductive layer to make the area less wettable.
25. The semiconductor device of claim 20 , wherein the first conductive layer includes an interconnect site comprising a maximum width less than 120% of a width of the first conductive layer away from the interconnect site.
26. A semiconductor device, comprising:
a first substrate including a first conductive layer; and
a composite interconnect structure reflowed and self-confined over the first conductive layer.
27. The semiconductor device of claim 26 , wherein the composite interconnect structure includes a fusible portion and a non-fusible portion.
28. The semiconductor device of claim 26 , wherein a width of the first conductive layer is less than a width of the composite interconnect structure.
29. The semiconductor device of claim 26 , wherein the first substrate includes a semiconductor die.
30. The semiconductor device of claim 26 , further including a second substrate including a second conductive layer disposed over the composite interconnect structure.