Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.
1. A method comprising:
applying a first voltage to a first line of a device during a memory operation performed on a first plurality of non-volatile memory cells and a second plurality of non-volatile memory cells of the device, the first plurality of non-volatile memory cells arranged in a first string, the second plurality of non-volatile memory cells arranged in a second string, wherein the first plurality of non-volatile memory cells are coupled to the first line through a base of a first bipolar junction transistor of the device, the second plurality of nonvolatile memory cells are coupled to the first line through a base of a second bipolar junction transistor of the device, the first plurality of non-volatile memory cells coupled between the first line and a second line, the second plurality of non-volatile memory cells coupled between the first line and the second line, and wherein the second line includes a data line and the first line includes a source line; and
applying a second voltage to the base of each of the first and second bipolar junction transistors during the memory operation, wherein the memory operation includes an erase operation.
2. A method comprising:
applying a first voltage to a first line of a device during an erase operation performed on a first plurality of non-volatile memory cells and a second plurality of non-volatile memory cells of the device, the first plurality of non-volatile memory cells arranged in a first string, the second plurality of non-volatile memory cells arranged in a second string; and
applying a second voltage to a base of a first bipolar junction transistor coupled between the first line and the first plurality of non-volatile memory cells and to a base of a second bipolar junction transistor coupled between the first line and the second plurality of non-volatile memory cells, the first plurality of non-volatile memory cells coupled to a second line, the second plurality of non-volatile memory cells coupled to the second line, wherein the second line includes a data line and the first line includes a source line, wherein the first voltage includes a first value, and the second voltage includes a second value greater than the first value.
3. The method of claim 2 , further comprising:
coupling the first line to a ground potential during a programming operation performed on the first plurality of non-volatile memory cells.
4. The method of claim 3 , further comprising:
coupling the base to a ground potential during the programming operation performed on the first plurality of non-volatile memory cells.
5. The method of claim 2 , further comprising:
placing the base in a float condition during a programming operation performed on the first plurality of non-volatile memory cells.
6. The method of claim 2 , further comprising:
coupling the base to a ground potential during a read operation performed on the first plurality of non-volatile memory cells.
7. A method comprising:
applying a first voltage to a conductive line of a device during an erase operation performed on a plurality of memory cells of the device; and
applying a second voltage to a base of a bipolar junction transistor coupled between the conductive line and the plurality of memory cells, wherein the first voltage includes a first magnitude value, the second voltage includes a second magnitude value, and the first value is greater than the second magnitude value.
8. The method of claim 7 , wherein the conductive line includes a source line.
9. A method comprising:
applying a first voltage to a source line of a device during a memory operation performed on a first plurality of memory cells and a second plurality of memory cells of the device, the first plurality of non-volatile memory cells arranged in a first string, the second plurality of non-volatile memory cells arranged in a second string, the first plurality of memory cells coupled between a first select transistor and a first bipolar junction transistor, the first select transistor coupled to a data line, the first bipolar junction transistor coupled to the source line, the second plurality of memory cells coupled between a second select transistor and a second bipolar junction transistor, the second select transistor coupled to the data line, the second bipolar junction transistor coupled to the source line; and
applying a second voltage to a base of each of the first and second bipolar junction transistors during the memory operation.
10. The method of claim 9 , wherein the memory operation includes a read operation.
11. The method of claim 9 , wherein the memory operation includes a programming operation.
12. The method of claim 9 , wherein the first voltage includes a first value, the second voltage includes a second value, and the second value is greater than the first value.
13. The method of claim 9 , wherein the first voltage includes a first value, the second voltage includes a second value, and the first value is greater than the second value.
14. The method of claim 9 , wherein each of first and second voltages includes a positive value.
15. The method of claim 9 , further comprising:
coupling the source line to a ground potential during the memory operation.
16. The method of claim 9 , further comprising:
coupling the base line to a ground potential during the memory operation.