System and method for manufacturing self-aligned STI with single poly
View Patent ↗A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
1. A method for manufacturing a memory device, the method comprising:
performing a shallow trench isolation process on a semiconductor material to form a plurality of active regions over the semiconductor material, the plurality of active regions having a plurality of sharp corners;
forming a plurality of isolation regions separating the plurality of active regions, the plurality of sharp corners of the plurality of active regions being exposed during the forming of the plurality of isolation regions;
rounding the plurality of sharp corners;
filling the plurality of isolation regions with an insulator material;
forming a plurality of charge trapping structures over the plurality of active regions, wherein the plurality of charge trapping structures are self-aligned, are separated from each other, and wherein each charge trapping structure corresponds specifically to a different active region of the plurality of active regions; and
forming a first layer of semiconductor or conductive material over the charge trapping structure.
2. The method of claim 1 , wherein the charge trapping structure is self-aligned by:
fabricating a bottom oxide layer;
depositing a SiRN layer;
depositing a sacrificial top oxide layer;
removing at least some portion of the top oxide layer;
performing a sacrificial oxide recess; and
etching to separate the SiRN layer between a plurality of cells.
3. The method of claim 1 further comprising:
performing the shallow trench isolation process before forming the charge trapping structure to expose corners of the active region so that the exposed corners can be rounded through a rounding process.
4. The method of claim 3 further comprising performing at least one liner oxide process to round the exposed corners of the active region.
5. The method of claim 3 further comprising performing at least one cleaning process to round the exposed comers of the active region.
6. The method of claim 1 wherein forming the charge trapping structure comprises:
forming a bottom oxide layer over the active region;
forming a nitride layer over the first oxide layer; and
forming a top block oxide layer over the nitride layer.
7. The method of claim 6 , wherein the nitride layer is comprised of silicon rich nitride.
8. The method of claim 6 , wherein the nitride layer is comprised of nitride on top of silicon rich nitride.
9. The method of claim 6 , wherein the nitride layer is comprised of multiple layers of nitride having different percentages of silicon content.
10. The method of claim 1 further comprising a plurality of periphery integration schemes.
11. The method of claim 10 , wherein a first periphery integration scheme comprises:
fabricating a top oxide layer;
masking an ONO structure;
etching the ONO structure;
fabricating a first periphery gate oxide layer;
etching the periphery gate oxide layer; and
fabricating a second periphery gate oxide layer, wherein the second periphery gate oxide layer is thinner than the first periphery gate oxide layer.
12. The method of claim 10 , wherein a second periphery integration scheme comprises:
depositing a nitride layer;
masking an ONO structure;
etching the ONO structure;
fabricating a first periphery gate oxide layer;
fabricating a top oxide layer;
masking the gate oxide layer;
etching the gate oxide; and
fabricating a second periphery gate oxide layer.