Electronic device including a capacitor structure and a process of forming the same
An electronic device can include a capacitor structure. In an embodiment, the electronic device can include a buried conductive region, a semiconductor layer having a primary surface, a horizontally-oriented doped region adjacent to the primary surface, an insulating layer overlying the horizontally-oriented doped region, and a conductive electrode overlying the insulating layer. The capacitor structure can include a first capacitor electrode including a vertical conductive region electrically connected to the horizontally-oriented doped region and the buried conductive region. The capacitor structure can further include a capacitor dielectric layer and a second capacitor electrode within a trench. The capacitor structure can be spaced apart from the conductive electrode. In another embodiment, an electronic device can include a first transistor, a trench capacitor structure, and a second transistor, wherein the first transistor is coupled to the trench capacitor structure, and the second transistor does not have a corresponding trench capacitor structure.
1. An electronic device comprising:
a buried conductive region;
a semiconductor layer having a primary surface and an opposing surface, wherein the buried conductive region is disposed closer to the opposing surface than to the primary surface, and the semiconductor layer defines a first trench having a sidewall and being adjacent to the primary surface and extending toward the buried conductive region;
a first horizontally-oriented doped region adjacent to the primary surface, wherein the first horizontally-oriented doped region is at least part of a drain region or a collector of a first transistor structure;
a first insulating layer overlying the first horizontally-oriented doped region;
a conductive electrode overlying the first insulating layer;
a first capacitor structure including:
a first capacitor electrode including a first vertical conductive region adjacent to the sidewall of the first trench and extending toward the buried conductive region, wherein the vertical conductive region is electrically connected to the first horizontally-oriented doped region and the buried conductive region;
a capacitor dielectric layer; and
a second capacitor electrode within the first trench,
wherein the first capacitor structure is spaced apart from and does not underlie the conductive electrode, and wherein the electronic device comprises a power transistor.
2. The electronic device of claim 1 , wherein the first capacitor electrode is disposed between the capacitor dielectric layer and the sidewall of the first trench.
3. The electronic device of claim 1 , wherein the first capacitor dielectric layer abuts the sidewall of the first trench.
4. The electronic device of claim 1 , further comprising:
a gate electrode or a base region of the first transistor structure; and
a source region or an emitter of the first transistor structure, wherein the conductive electrode is electrically connected to the source or emitter region.
5. The electronic device of claim 1 , wherein the capacitor dielectric layer comprises a nitride film.
6. The electronic device of claim 5 , wherein the capacitor dielectric layer further comprises an oxide film.
7. The electronic device of claim 6 , wherein the oxide film is disposed between the first capacitor electrode and the nitride film.
8. The electronic device of claim 1 , wherein:
the conductive electrode has a first portion that lies substantially along a first plane and a second portion having a height that is substantially perpendicular to the first plane; and
the second capacitor electrode has an uppermost location at an elevation higher than a highest elevation of the first portion of the conductive electrode.
9. The electronic device of claim 8 , wherein a same conductive plug abuts the second capacitor electrode and the second portion of the conductive electrode.
10. The electronic device of claim 4 , further comprising:
a second transistor structure including a second horizontally-oriented doped region adjacent to the primary surface; and
a vertical conductive region that is electrically connected to the second horizontally-oriented doped region and the buried conductive region, wherein the vertical conductive region is not part of any trench capacitor structure having a capacitor dielectric layer.
11. The electronic device of claim 10 , wherein:
the semiconductor layer further defines a second trench having a sidewall, wherein the second trench is adjacent to the primary surface and extends toward the buried conductive region; and
the vertical conductive region comprises a vertical conductive structure that substantially completely fills a remaining portion of the second trench.
12. The electronic device of claim 11 , wherein the first capacitor electrode only partly, and not completely, fills the first trench.
13. The electronic device of claim 10 , wherein the first and second transistor structures are at least part of power transistors.
14. A process of forming an electronic device comprising:
providing a workpiece including a buried conductive region and a semiconductor layer over the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface, and wherein the buried conductive region is disposed closer to the opposing surface than to the primary surface;
forming a horizontally-oriented doped region adjacent to the primary surface, wherein the horizontally-oriented doped region is at least part of a drain region or a collector of a transistor structure;
forming a conductive electrode adjacent to the primary surface;
forming a gate electrode of a transistor structure; and
forming a trench capacitor structure after forming the gate electrode, wherein the trench capacitor is electrically connected to the buried conductive region and a current-carrying electrode of the transistor structure, and wherein the trench capacitor is spaced apart from the conductive electrode.
15. The process of claim 14 , wherein forming the trench capacitor structure comprises:
patterning the semiconductor layer to define a trench adjacent to the primary surface and extending toward the buried conductive region;
forming a capacitor dielectric layer within the trench; and
forming a first capacitor electrode within the trench after forming the capacitor dielectric layer.
16. The process of claim 15 , wherein the forming the trench capacitor structure further comprises forming a second capacitor electrode within the trench before forming the capacitor dielectric layer.
17. The process of claim 16 , wherein the horizontally-oriented doped region is formed adjacent to the trench and the second capacitor electrode.
18. The process of claim 15 , wherein forming the trench capacitor structure further comprises forming a second capacitor electrode that includes a doped portion of the semiconductor layer that extends to the buried conductive region.
19. An electronic device comprising:
a buried conductive region;
a semiconductor layer having a primary surface and an opposing surface, wherein the buried conductive region is disposed closer to the opposing surface than to the primary surface, and the semiconductor layer defines a first trench having a sidewall and being adjacent to the primary surface and extending toward the buried conductive region;
a first horizontally-oriented doped region adjacent to the primary surface;
a first insulating layer overlying the first horizontally-oriented doped region;
a conductive electrode overlying the first insulating layer;
a first capacitor structure including:
a first capacitor electrode including a first vertical conductive region adjacent to the sidewall of the first trench and extending toward the buried conductive region, wherein the vertical conductive region is electrically connected to the first horizontally-oriented doped region and the buried conductive region;
a capacitor dielectric layer; and
a second capacitor electrode within the first trench,
wherein:
the first capacitor structure is spaced apart from and does not underlie the conductive electrode;
the conductive electrode has a first portion that lies substantially along a first plane and a second portion having a height that is substantially perpendicular to the first plane; and
the second capacitor electrode has an uppermost location at an elevation higher than a highest elevation of the first portion of the conductive electrode.