Devices and methods for measurement of magnetic characteristics of MRAM wafers using magnetoresistive test strips
Methods for testing magnetoresistance of test devices with layer stacks, such as MTJs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing. The test devices with contact pads at opposite ends of the bottom electrode allow resistance across the bottom electrode to be measured as a surrogate for measuring resistance between the top and bottom electrodes. An MTJ test device according to the invention has a measurable magnetoresistance (MR) between the two contact pads that is a function of the magnetic orientation of the free layer and varies with the length and width of the MTJ strip in each test device. The set of test MTJs can include a selected range of lengths to allow the tunnel magnetoresistance (TMR) and resistance area product (RA) to be estimated or predicted.
1. A method of testing magnetoresistive devices on a wafer:
fabricating a set of magnetoresistive test devices on the wafer that includes magnetoresistive test devices having a plurality of lengths as measured along a surface plane of the wafer, with each magnetoresistive test device having a high and a low electrical resistance state as measured through a plurality of layers in the magnetoresistive test device that depends on a switchable first and second magnetization orientations of a free magnetic layer and each test device including an electrode layer that spans between and makes electrical contact with a corresponding pair of electrically conductive pads;
applying a first selected magnetic field to the set of magnetoresistive test devices to set the free magnetic layers to have the first magnetization orientation;
measuring a first electrical resistance between the corresponding pair of electrically conductive pads for each of the magnetoresistive test devices while the free magnetic layer has the first magnetization orientation;
applying a second selected magnetic field to the set of magnetoresistive test devices to set the free magnetic layers to have the second magnetization orientation;
measuring a second electrical resistance between the corresponding pair of electrically conductive pads for each of the magnetoresistive test devices while the free magnetic layer has the second magnetization orientation; and
calculating a magnetoresistance value for each magnetoresistive test device.
2. The method of claim 1 wherein measuring the first electrical resistance further comprises placing a test probe in contact with electrically conductive pads on a surface of the wafer that are electrically connected to the corresponding pair of electrically conductive pads.
3. The method of claim 1 further comprising comparing the magnetoresistance values for the magnetoresistive test devices with predetermined thresholds to determine whether electrical shorting exists in the magnetoresistive test devices.
4. The method of claim 1 further comprising using the first and second electrical resistance values corresponding to first and second magnetization orientations of the free layer, the magnetoresistance values and the corresponding lengths for the set of magnetoresistive test devices to derive a magnetoresistance curve.
5. The method of claim 1 further comprising using the first and second electrical resistance values corresponding to first and second magnetization orientations of the free layer, the magnetoresistance values and the corresponding lengths for the set for the magnetoresistive test devices to derive a resistance area product.
6. The method of claim 1 wherein the wafer includes a plurality of magnetic tunnel junction memory devices that are arranged in an array and have a layer structure that is substantially equal to a layer structure of the magnetoresistive test devices and wherein the magnetoresistance values for the set of magnetoresistive test device are used to test of quality of preceding fabrication steps before executing additional fabrication steps.
7. The method of claim 6 further comprising performing a series of process steps to connect the magnetic tunnel junction memory devices in the array to bit lines.
8. The method of claim 6 wherein one magnetic tunnel junction test device has a length measured along a line between the corresponding pair of electrically conductive contact pads that is substantially greater than a feature size of the magnetic tunnel junction memory devices that are arranged in the array.
9. The method of claim 6 wherein the magnetoresistive test devices are formed in strips that have a length measured along a line between the corresponding contact pads that is substantially greater than a width measured perpendicular to the line.