Structure for self-aligned silicide contacts to an upside-down FET by epitaxial source and drain
An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region.
1. An integrated circuit device comprising:
a donor substrate comprising a silicon substrate, a buried oxide, and a single-crystal silicon-on-insulator layer; and
an upside down p-FET disposed on the donor substrate, said upside-down p-FET comprising:
self-terminating e-SiGe source and drain regions;
a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions;
a silicon channel region connecting the e-SiGe source and drain regions;
buried oxide above the silicon channel region;
a gate controlling a current flow from the e-SiGe source region to the e-SiGe drain region, said gate comprising a thin gate dielectric layer over the silicon-on-insulator layer and a gate conductor line over said thin gate dielectric layer;
a first stress liner deposited over the gate and the e-SiGe source and drain regions; and
wherein at least a portion of said e-SiGe source and drain regions and the buried oxide are exposed upon removal of the donor substrate.
2. The integrated circuit device of claim 1 further comprising:
contacts formed through the dielectric to the protruding e-SiGe source and drain regions such that the first stress liner is not impinged.
3. The integrated circuit device of claim 1 further comprising a low k-dielectric formed over the first stress liner.
4. The integrated circuit device of claim 1 further comprising a second stress liner disposed under the e-SiGe source and drain regions.