Multi-level cells and method for using the same
View Patent ↗The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.
1. A method for detecting individual resistance states of a plurality of memory elements coupled in series in a memory device, each of the plurality of memory elements having a resistance state and can be switched from a first resistance level to a second resistance level by a write input no lower than a write threshold, the method comprising the steps of:
sequentially writing at least one of the plurality of memory elements from the resistance state thereof to the second resistance level in order of ascending write threshold;
ascertaining whether each of the at least one of the plurality of memory elements has switched from the first resistance level to the second resistance level;
concluding the resistance state of the each of the at least one of the plurality of memory elements is in the first resistance level if the each of the at least one of the plurality of memory elements has switched; and
concluding the resistance state of the each of the at least one of the plurality of memory elements is in the second resistance level if the each of the at least one of the plurality of memory elements has not switched.
2. The method of claim 1 , further comprising the step of sequentially writing each of the at least one of the plurality of memory elements to the resistance state thereof from the second resistance level in order of descending write input threshold.
3. The method of claim 1 , wherein each of the plurality of memory elements includes a magnetic tunnel junction with a write input associated therewith, the write input comprises at least one current or voltage pulse characterized by a pulse amplitude and a pulse length.
4. The method of claim 3 , wherein the step of sequentially writing at least one of the plurality of memory elements to the second resistance level in order of ascending write threshold further includes the step of reducing coercivity of the magnetic tunnel junction of the at least one of the plurality of memory elements by an external means during writing.
5. The method of claim 4 , wherein the external means is heating, applying mechanical stress, or applying an electric or magnetic field to the magnetic tunnel junction.
6. The method of claim 1 , wherein the plurality of memory elements are made of magnetic tunnel junctions with the write thresholds associated therewith having different current thresholds or voltage thresholds at the substantially same pulse length.
7. A method for detecting individual resistance states of a plurality of memory elements coupled in series in a memory device, each of the plurality of memory elements having a resistance state that can be switched from a first resistance level to a second resistance level by a first write input no lower than a first write threshold and can be switched from the second resistance level to the first resistance level by a second write input no lower than a second write threshold, the method comprising the steps of:
sequentially writing at least one of the plurality of memory elements to a corresponding individual target resistance state in order of ascending write threshold, the corresponding individual target resistance state being either the first or second resistance level;
ascertaining whether each of the at least one of the plurality of memory elements has switched the resistance state thereof;
concluding the each of the at least one of the plurality of memory elements is in a different resistance level from the corresponding individual target resistance state if the each of the at least one of the plurality of memory elements has switched the resistance state thereof; and
concluding the each of the at least one of the plurality of memory elements is in the corresponding individual target resistance state if the each of the at least one of the plurality of memory elements has not switched the resistance state thereof.
8. The method of claim 7 , further comprising the step of sequentially writing each of the at least one of the plurality of memory elements to the resistance state thereof from the corresponding individual target resistance state in order of descending write input threshold.
9. A memory device with multiple memory sectors, the memory device comprising a plurality of memory cells with each memory cell including a plurality of memory elements coupled in series, wherein at least one of the plurality of memory cells has the plurality of memory elements thereof divided between at least two memory sectors that have different access speeds.
10. The memory device of claim 9 , wherein the plurality of memory elements have different write input thresholds.
11. The memory device of claim 9 , wherein each of the plurality of memory elements has two resistance levels.
12. The memory device of claim 9 , wherein each of the plurality of memory elements includes a magnetic tunnel junction.
13. The memory device of claim 9 , wherein each of the at least two memory sectors includes at least one of the plurality of memory elements from each of the plurality of memory cells.
14. The memory device of claim 13 , wherein the plurality of memory elements have different write input thresholds.
15. The memory device of claim 13 , wherein each of the plurality of memory elements has two resistance levels.
16. The memory device of claim 13 , wherein each of the plurality of memory elements includes a magnetic tunnel junction.