IP Library Granted Patent US 9,461,026
Granted Patent B2
US 9,461,026 · App. 14/245,191 · Granted Oct 4, 2016

Method and system for template assisted wafer bonding

Inventors: John Dallesasse (Geneva, IL); Stephen B. Krasulick (Albuquerque, NM)
Assignee: Skorpios Technologies, Inc.
H01L25/167H01L21/78H01L21/822H01L23/50H01L24/97H01L31/1876H01L33/005H01L33/48H01L33/52H01L2924/1204H01L2924/12042H01L2924/14H01S5/026H01S5/0217
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Quick Facts
Patent No.
US 9,461,026
App. No.
14/245,191
Granted
Oct 4, 2016
Kind
B2
Abstract

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Claims (25)

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a first substrate having a device surface and one or more semiconductor devices thereon;

providing a second substrate having epitaxial compound semiconductor materials;

dicing the second substrate to provide a plurality of compound semiconductor seed dies;

bonding at least one of the plurality of compound semiconductor seed dies to the first substrate to form the composite semiconductor structure; and

growing epitaxial compound semiconductor layers on the at least one of the plurality of compound semiconductor seed dies.

2. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein:

the device surface is part of a device layer of a silicon-on-insulator (SOI) wafer;

the SOI wafer comprises a silicon-dioxide layer under the device surface; and

the SOI wafer comprises a silicon handle under the silicon-dioxide layer.

3. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the one or more semiconductor devices comprise at least one of a CMOS device, a BiCMOS device, an NMOS device, a PMOS device, a detector, a CCD, or an optics device.

4. The method of fabricating the composite semiconductor structure as recited in claim 1 , further comprising:

mounting the at least one of the plurality of compound semiconductor seed dies to a third substrate; and

removing the third substrate from the least one of the plurality of compound semiconductor seed dies after bonding the at least one of the plurality of compound semiconductor seed dies to the first substrate.

5. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the composite semiconductor structure comprises one or more photonic devices, wherein the one or more photonic devices includes a laser, a detector, a modulator, an optical isolator, and/or an optical circulator.

6. The method of fabricating the composite semiconductor structure as recited in claim 1 , the method further comprising bonding the plurality of compound semiconductor seed dies to the first substrate.

7. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein:

the first substrate is etched to form a pit; and

at least one of the plurality of compound semiconductor seed dies is bonded in the pit.

8. The method of fabricating the composite semiconductor structure as recited in claim 7 , wherein the at least one of the plurality of compound semiconductor seed dies is covered after being bonded in the pit.

9. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the plurality of compound semiconductor seed dies comprise III-V or II-VI material.

10. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the first substrate comprises silicon.

11. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the first substrate comprises optical elements formed in silicon.

12. The method of fabricating the composite semiconductor structure as recited in claim 11 further comprising, after growing epitaxial compound semiconductor layers, fabricating gate metals on doped regions of the first substrate.

13. The method of fabricating the composite semiconductor structure as recited in claim 1 , further comprising defining one or more functional elements on the at least one of the plurality of compound semiconductor seed dies after bonding the at least one of the plurality of compound semiconductor seed dies to the first substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 044272/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2014
From: DALLESASSE, JOHN; KRASULICK, STEPHEN B.
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 034064/0767 →
Continuity (5)
Continuation 13869408 · Apr 24, 2013
Continuation 13527394 · Jun 19, 2012
Continuation 13112142 · May 20, 2011
Provisional Application 61420917 · Dec 8, 2010
Related Publication 20140342500A1 · Nov 20, 2014