Smart bridge for memory core

1. An apparatus comprising:

a semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate,

wherein the 3D memory includes circuitry associated with operation of the multiple memory cells, and

wherein the semiconductor die that includes the 3D memory includes a serializer/deserializer interface configured to enable communication, via a second semiconductor die that is coupled to the serializer/deserializer interface, with a controller of the 3D memory, the controller on a third semiconductor die that is distinct from the second semiconductor die, wherein the second semiconductor die includes periphery circuitry configured to scramble data received from the controller and to communicate the scrambled data to the semiconductor die via the serializer/deserializer interface.

2. The apparatus of claim 1 , wherein the controller includes another serializer/deserializer interface.

3. The apparatus of claim 1 , wherein the second semiconductor die further comprises peripheral circuitry coupled to the 3D memory, the peripheral circuitry including another serializer/deserializer interface.

4. The apparatus of claim 1 , wherein the substrate is a silicon substrate.

5. The apparatus of claim 1 , wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store write data into memory cells of the 3D memory and to be responsive to a read instruction to retrieve read data from the memory cells of the 3D memory.

6. An apparatus comprising:

a first semiconductor die including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells; and

a second semiconductor die coupled to the first semiconductor die, the second semiconductor die including periphery circuitry associated with the 3D memory, the second semiconductor die including a second serializer/deserializer communication interface that is coupled to a first serializer/deserializer communication interface of a memory controller of the 3D memory, the periphery circuitry configured to scramble data received from the memory controller via the second serializer/deserializer communication interface, wherein the memory controller is included on a third semiconductor die that is distinct from the first semiconductor die and the second semiconductor die.

7. The apparatus of claim 6 , wherein the first semiconductor die is wire bonded to the second semiconductor die.

8. The apparatus of claim 6 , wherein the first semiconductor die and the second semiconductor die are in a common package.

9. The apparatus of claim 6 , wherein the substrate is a silicon substrate.

10. The apparatus of claim 6 , wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store data into memory cells of the 3D memory and to be responsive to a read instruction to read data from the memory cells of the 3D memory.

11. A method comprising:

receiving a serial stream of data symbols at a serializer/deserializer interface of a semiconductor device including a three-dimensional (3D) memory that includes multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate, wherein the 3D memory includes circuitry associated with operation of the multiple memory cells, the serial stream of data symbols representing scrambled data, the scrambled data generated by periphery circuitry of a second semiconductor device that is coupled to the serializer/deserializer interface, wherein the periphery circuitry generates the scrambled data based on write data received by the second semiconductor device from a memory controller; and

deserializing the serial steam of data symbols to generate data to be stored at the 3D memory.

12. The method of claim 11 , wherein the peripheral circuitry includes a second serializer/deserializer interface.

13. The method of claim 12 , wherein the write data is received at the second semiconductor device via another serializer/deserializer interface.

14. The method of claim 11 , wherein the substrate is a silicon substrate.

15. The method of claim 11 , wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store the data into memory cells of the 3D memory and to be responsive to a read instruction to read the data from the memory cells of the 3D memory.

16. A method comprising:

receiving a serial stream of data symbols at a serializer/deserializer interface of a second semiconductor device, wherein the second semiconductor device includes periphery circuitry for a three-dimensional (3D) memory at a first semiconductor device, the 3D memory including multiple memory cells arranged in multiple physical levels that are monolithically formed above a substrate and including circuitry associated with operation of the multiple memory cells;

deserializing the serial steam of data symbols to generate data to be stored at the 3D memory;

scrambling the data at the periphery circuitry to generate scrambled data; and

sending a control signal from the second semiconductor device to the 3D memory, wherein the control signal corresponds to storing the scrambled data at the 3D memory.

17. The method of claim 16 , wherein the serial stream of data symbols is received from a memory controller coupled to the second semiconductor device via a second serializer/deserializer interface.

18. The method of claim 16 , wherein the second semiconductor device is coupled to the first semiconductor device via another serializer/deserializer interface.

19. The method of claim 16 , wherein the substrate is a silicon substrate.

20. The method of claim 16 , wherein the circuitry associated with operation of the multiple memory cells is configured to be responsive to a write instruction to store write data into memory cells of the 3D memory and to be responsive to a read instruction to retrieve read data from the memory cells of the 3D memory.