Multi-step deep reactive ion etching fabrication process for silicon-based terahertz components
A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.
1. A method of manufacturing a silicon waveguide circuit element, comprising the steps of:
providing a silicon wafer having a surface comprising a flat surface;
providing a SiO 2 layer having an initial thickness on said surface;
etching a plurality N of patterns in said SiO 2 layer, to form a plurality N of SiO 2 patterns having a respective thickness representing a respective depth of etching into said silicon wafer, said respective thicknesses being different from one another, where N is an integer greater than one; and
repeating a total of N times in succession the two steps of:
(1) performing an SiO 2 etch simultaneously on all of said plurality N of SiO 2 patterns to expose one or more respective regions of said surface of said silicon wafer beneath a thinnest remaining one of said plurality N of SiO 2 patterns; and
(2) performing a silicon etch simultaneously on said silicon wafer below all of said exposed respective regions of said surface of said silicon wafer, wherein said exposed respective regions are etched down by a depth comprising a difference between said respective depth, associated with said thinnest remaining one of said plurality N of SiO 2 patterns, and said respective depth associated with a next thinnest remaining one of said plurality N of SiO 2 patterns;
wherein:
each of said plurality N of patterns are etched down into said silicon wafer to their respective depth of etching, and a multi depth structure in said silicon wafer is formed.
2. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein the step of providing said SiO 2 layer on said surface is performed by plasma-enhanced chemical vapor deposition.
3. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein the step of providing said SiO 2 layer on said surface is performed by thermal growth of SiO 2 .
4. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein said initial thickness of said SiO 2 layer is sufficient to provide a safety margin after said plurality N of patterns are etched in said SiO 2 layer.
5. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein said step of performing an SiO 2 etch is done using an inductively coupled plasma.
6. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein said step of performing said silicon etch is done using deep reactive ion etching.
7. The method of manufacturing said silicon waveguide circuit element of claim 6 , wherein said deep reactive ion etching is performed using SF 6 .
8. The method of manufacturing said silicon waveguide circuit element of claim 7 , wherein said deep reactive ion etching is followed by a step comprising exposing said silicon wafer to C 4 F 8 gas.
9. The method of manufacturing said silicon waveguide circuit element of claim 1 , wherein said respective depths etched into said silicon wafer are controlled to within 2% of depth targets for said respective depths.
10. The method of claim 1 , wherein said silicon waveguide circuit element is a terahertz silicon waveguide circuit element comprising said multi depth structure.
11. The method of claim 10 , wherein said multi depth structure includes a cross section of a waveguide that is rectangular.
12. The method of claim 1 , wherein:
for the first repeating of said two steps, said thinnest remaining one of said plurality N of SiO 2 patterns has said respective thickness representing a deepest of said respective depths of etching into said silicon wafer, and
for the final repeating of said two steps, said thinnest remaining one of said plurality N of SiO 2 patterns has said respective thickness representing a shallowest of said respective depths of etching into said silicon wafer.
13. A method of fabricating a silicon waveguide component, comprising:
providing at least one mask on silicon, the at least one mask including a plurality N of patterns, the patterns each:
associated with a different thickness of the mask designed to achieve a different depth of etching into the silicon, where N is an integer; and
indexed with an integer j, wherein 1≦j≦N and the j th pattern is designed to achieve a deeper depth of etching than the j+1 th pattern;
performing N etch steps each indexed with an integer k, wherein:
1≦k≦N and the etch steps are performed in order of increasing k, and
during the k th etch step, the silicon is etched with all the one or more j th patterns, wherein j≦k, by a depth comprising a difference between the depth associated with the j th pattern wherein j=k and the depth associated with the j th pattern wherein j=k+1; and
wherein each pattern is etched down into the silicon such that the j th pattern is etched down to the depth associated with the j th pattern and the waveguide component comprising a multi depth structure in the silicon is formed.
14. The method of claim 13 , wherein the silicon is etched using deep reactive ion etching.
15. The method of claim 13 , wherein the silicon waveguide component is a silicon terahertz waveguide.
16. The method of claim 15 , wherein the silicon terahertz waveguide has an insertion loss that is decreased as compared to insertion loss for a silicon terahertz waveguide fabricated using a process wherein structures in the silicon terahertz waveguide are etched to their final depth in the silicon in a single etch step.
17. The method of claim 15 , wherein the silicon terahertz waveguide hosts a mixer.
18. A method of fabricating a silicon waveguide component, comprising:
providing a mask including a plurality of patterns;
gradually etching the plurality of the patterns into silicon using a plurality of etch steps, wherein:
the patterns are each etched to an etch depth in the silicon;
the patterns are etched in a succession starting with the pattern being etched to a deepest etch depth and ending with the pattern being etched to a shallowest etch depth and such that each of the patterns are etched down with a next one of the patterns, and
each etch step etches a depth difference between the patterns until all the patterns are etched to their etch depth.