Group word line erase and erase-verify methods for 3D non-volatile memory
An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
1. A method for performing an erase operation, comprising:
charging a channel of an active area of a plurality of memory cells, the charging of the channel comprises applying an erase voltage to one end of the active area, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory;
during the charging of the channel, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, the setting the control gate voltages is based on an assignment of the plurality of memory cells to different groups, each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells;
performing an erase-verify test for the plurality of memory cells; and
before the applying of the erase voltage, pre-charging the channel by applying a pre-charge voltage which is lower than the erase voltage to the one end of the active area, the pre-charge voltage charges the channel by gate-induced drain leakage of a select gate at the one end of the active area.
2. The method of claim 1 , wherein:
the control gate voltages are different for each group of the different groups and common within each group; and
the erase-verify test is performed concurrently for the different groups.
3. The method of claim 2 , wherein:
the erase-verify test is performed concurrently for the different groups by applying a common erase-verify control gate voltage to the plurality of memory cells while detecting a current through the active area.
4. The method of claim 2 , wherein:
for each group, the control gate voltage is a function of a distance of the group from the one end of the active area.
5. The method of claim 4 , wherein:
the control gate voltage decreases with a distance of the group from the one end of the active area.
6. The method of claim 1 , wherein:
the control gate voltages are common for each group of the different groups; and
the erase-verify test is performed one group at a time for the different groups.
7. The method of claim 6 , wherein the charging of the channel and the setting the control gate voltages occur in an erase portion of one erase-verify iteration, the method further comprising:
providing an erase status=inhibit for one or more groups of the different groups which pass the erase-verify test;
providing an erase status=erase for remaining groups of the different groups which do not pass the erase-verify test; and
in an erase portion of a subsequent erase-verify iteration, for the one or more groups which have the erase status=inhibit, floating the control gate voltagesof memory cells in the one or more groups and, for the remaining groups of the different groups which do not pass the erase-verify test, setting the control gate voltages at a level which encourages erasing of memory cells in the one or more groups.
8. The method of claim 6 , wherein:
for each group, the erase-verify test is performed by applying an erase-verify control gate voltage to memory cells in the group and applying a pass voltage to memory cells in remaining groups while detecting a current through the active area, the erase-verify control gate voltage is common among the groups.
9. The method of claim 1 , wherein:
the control gate voltages encourage erasing of the memory cells by being sufficiently low compared to a voltage in the channel to induce tunneling of holes from the channel into charge trapping regions of the memory cells.
10. The method of claim 1 , wherein:
the charging of the channel, the setting of the control gate voltages and the performing of the erase-verify test are performed by circuitry which is associated with operation of the plurality of memory cells and the circuitry is within the substrate.
11. The method of claim 1 , wherein:
the charging of the channel, the setting of the control gate voltages and the performing of the erase-verify test are performed by circuitry which is associated with operation of the plurality of memory cells and the circuitry is above the substrate.
12. A non-volatile memory device, comprising:
a substrate;
a plurality of memory cells comprising an active area, the active area comprising a channel, the plurality of memory cells are formed above the substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the plurality of memory cells are subdivided into different groups based on group assignments, and each group of the different groups comprises multiple adjacent memory cells of the plurality of memory cells, wherein the active area is U-shaped and comprises two pillars which extend vertically in the three-dimensional non-volatile memory, and the groups extend from one end of the active area to a back gate of the active area; and
circuitry coupled with the plurality of memory cells, the circuitry, to perform an erase operation for the plurality of memory cells is configured to: apply an erase voltage to one end of the active area to charge the channel, during the charging of the channel, set control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, and perform an erase-verify test for the plurality of memory cells, the setting the control gate voltages is based on the groups assignments.
13. The non-volatile memory device of claim 12 , wherein:
the control gate voltages are different for each group of the different groups and common within each group; and
the erase-verify test is performed concurrently for the different groups.
14. The non-volatile memory device of claim 12 , wherein:
the control gate voltages are common for each group of the different groups; and
the erase-verify test is performed one group at a time for the different groups.
15. The non-volatile memory device of claim 12 , wherein:
the channel is in a vertical memory hole.
16. The non-volatile memory device of claim 12 , wherein:
the circuitry is within the substrate.
17. The non-volatile memory device of claim 12 , wherein:
the circuitry is above the substrate.
18. A method for performing an erase operation, comprising:
applying an erase voltage to one end of an active area of a plurality of memory cells, the plurality of memory cells are formed above a substrate in multiple physical levels of memory cells in a three-dimensional non-volatile memory, the active area comprises a pillar which extends vertically in the three-dimensional non-volatile memory, the plurality of memory cells are assigned to different groups, and each group comprises multiple adjacent memory cells of the plurality of memory cells;
during the applying of the erase voltage, setting control gate voltages of the plurality of memory cells to encourage erasing of the memory cells, wherein the control gate voltages are common within each group; and
performing an erase-verify test for the plurality of memory cells.
19. The method of claim 18 , wherein:
the control gate voltage decreases with a distance of the group from the one end of the active area.
20. The method of claim 18 , wherein:
the control gate voltages are different for each group of the different groups.
21. The method of claim 18 , wherein:
the erase-verify test is performed one group at a time for the different groups, the applying the erase voltage, the setting of the control gate voltages and the performing of the erase-verify test are performed by circuitry which is associated with operation of the plurality of memory cells and the circuitry is within the substrate.
22. The method of claim 18 , wherein:
the erase-verify test is performed one group at a time for the different groups, the applying the erase voltage, the setting of the control gate voltages and the performing of the erase-verify test are performed by circuitry which is associated with operation of the plurality of memory cells and the circuitry is above the substrate.
23. The method of claim 6 , wherein the charging of the channel and the setting the control gate voltages occur in an erase portion of one erase-verify iteration, the method further comprising:
providing an erase status=inhibit for one or more groups of the different groups which pass the erase-verify test;
providing an erase status=erase for remaining groups of the different groups which do not pass the erase-verify test; and
in an erase portion of a subsequent erase-verify iteration, for the one or more groups which have the erase status=inhibit, driving the control gate voltages at a level which discourages erasing of memory cells in the one or more groups and, for the remaining groups of the different groups which do not pass the erase-verify test, setting the control gate voltages at a level which encourages erasing of memory cells in the one or more groups.