Emulation of static random access memory (SRAM) by magnetic random access memory (MRAM)

1. A magnetic memory system comprising:

a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command;

a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs, each of the magnetic memory banks being coupled to a respective one of the plurality of FIFOs, at least one FIFO of the plurality of FIFOs being operative to queue write commands on a per magnetic memory bank basis and further operative to issue queued write commands at a time when the MRAM is not in use, the FIFO interface device including a plurality of address blocks, a plurality of comparators, a plurality of data registers and a plurality of data selects, each of the plurality of address blocks being coupled to a data register of the data registers and responsive to an address identifying a location in the MRAM to write data to and each of the plurality of data registers being responsive to input data and coupled to one of the plurality of data selects and responsive to the address, each of the comparators being responsive to an output from one of the address blocks of the plurality of address blocks and operative to compare the same to the address and if no match is detected to output data from the MRAM and if a match is detected, to output data from the FIFO interface device, each of the plurality of FIFOs being operable to select one of the plurality of magnetic memory banks,

wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

2. The magnetic memory system, as recited in claim 1 , wherein the FIFO interface device checks data coherency to return data if the FIFO interface device holds the most recent data that is being accessed.

3. The magnetic memory system, as recited in claim 1 , wherein the FIFO interface device includes a pending read register for storing pending read commands and further wherein, when a read command is issued when a pending write operation is in progress, the read command is saved in pending read register and the contents of the pending read register becomes a pending read command, which is executed after completion of the pending write operation.

4. The magnetic memory system, as recited in claim 3 , wherein a signal is activated to indicate that the magnetic memory system is busy during at least some of the time the pending write operation is pending.

5. The magnetic memory system, as recited in claim 1 , wherein when a read command is issued and a write operation is in progress, the write operation that is in progress is aborted and the read operation is executed.

6. The magnetic memory system, as recited in claim 1 , wherein after a write command is issued, while the MRAM is idle and the FIFO interface device is not empty, the FIFO interface device is operative to save and further operative to send a pending command, previously saved in the FIFO interface device, to the MRAM to perform a write operation of the MRAM.

7. The magnetic memory system, as recited in claim 1 , wherein after a write command is issued and a write operation is in progress, the write command is saved and the write operation remains in progress.

8. The magnetic memory system, as recited in claim 1 , wherein after a write command is issued when the FIFO interface device is near full, the FIFO interface device activates a signal to indicate that the magnetic memory system is busy.

9. The magnetic memory system, as recited in claim 1 , wherein after a write command is issued and the FIFO interface device is near full, the FIFO interface device being operative to save the write command and to activate a signal to indicate that the magnetic memory system is busy, and if the MRAM is idle, the FIFO interface device being operative to send a pending command to the MRAM to perform a write operation thereof.

10. The magnetic memory system, as recited in claim 1 , wherein the FIFO interface device is operative to queue a pending write operation to the MRAM, a pending write operation ultimately initiating a write operation to MRAM, and upon completion of write operation to remove the write operation from a queue of pending write operations.

11. The magnetic memory system, as recited in claim 1 , wherein if a signal indicative of whether or not the magnetic memory system is busy is activated and the FIFO interface device is not near full, the signal is inactivated in the last cycle of the write operation.

12. The magnetic memory system, as recited in claim 1 , wherein the FIFO interface device is operative to generate a plurality of bank select signals, each of which is coupled to one of the MRAM banks of the plurality of MRAM banks for selecting one of the plurality of MRAM banks.

13. The magnetic memory system, as recited in claim 1 , wherein the FIFO interface device is operative to generate a bank select signal to the plurality of MRAM banks for selecting one of the MRAM banks of the plurality of MRAM banks.

14. An apparatus comprising:

digital circuitry;

volatile memory coupled to the digital circuitry;

analog circuitry coupled to the digital circuitry;

non-volatile memory coupled to the digital circuitry;

magnetic memory system coupled to the digital circuitry and including, a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command;

a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs, each of the magnetic memory banks being coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, the FIFO interface device including a plurality of address blocks, a plurality of comparators, a plurality of data registers and a plurality of data selects, each of the plurality of address blocks being coupled to a data register of the data registers and responsive to an address identifying a location in the MRAM to write data to and each of the plurality of data registers being responsive to input data and coupled to one of the plurality of data selects and responsive to the address, each of the comparators being responsive to an output from one of the address blocks of the plurality of address blocks and operative to compare the same to the address and if no match is detected to output data from the MRAM and if a match is detected, to output data from the FIFO interface device, each of the plurality of FIFOs being operable to select one of the plurality of magnetic memory banks, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks.

15. The magnetic memory system, as recited in claim 14 , wherein the FIFO interface device is operative to perform multiple write operations and to check data coherency to return data if the FIFO interface device holds the most recent data that is being accessed.

16. The magnetic memory system, as recited in claim 14 , wherein the FIFO interface device includes a pending read register for storing pending read commands and further wherein, during a read operation that is occurring at time when a pending write operation is in progress, the contents of the pending read register becomes a pending read command, which is executed after completion of the pending write operation.