Merged gate and source/drain contacts in a semiconductor device
Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.
1. A method of forming a semiconductor device, the method comprising:
forming a set of contact placeholders over both a set of fins and a capping layer over the set of fins, the set of contact placeholders comprising nitride atop an oxide;
providing a dielectric layer over a set of gate structures formed over a substrate and over the set of contact placeholders;
patterning a set of source/drain (S/D) openings in the dielectric layer between the set of gate structures;
removing the nitride from atop the oxide;
removing the oxide selective to the dielectric layer and the capping layer; and
forming a fill material over the set of gate structures, including within the set of S/D openings;
patterning a set of gate openings over the set of gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the set of S/D openings is removed, and at least one gate opening of the set of gate openings exposes on a bottom of the gate opening only a part or all of one gate structure of the set of gate structures;
removing the fill material selective to the dielectric layer; and
removing the capping layer from atop the set of gate structures within the set of gate openings and from atop the set of fins within the set of S/D openings.
2. The method according to claim 1 , further comprising depositing a metal material over the semiconductor device to form a set of gate contacts within the set of gate openings and a set of S/D contacts within the set of S/D openings, wherein at least one of the set of gate contacts and at least one of the set of S/D contacts are merged.
3. The method according to claim 1 , the patterning the set of gate openings comprising partially etching the capping layer atop the set of gate structures within the set of gate openings.
4. The method according to claim 1 , the dielectric layer comprising silicon oxycarbide (SiOC), and the fill material comprising a deep ultraviolet light absorbing oxide (DUO).
5. The method according to claim 4 , the DUO removed selective to the SiOC using an O2 plasma process (Ash).
6. The method according to claim 1 , wherein each of the set of gate openings has sloped sidewalk that converge towards the set of gate structures.
7. A method for forming merged gate and source/drain (S/D) contacts in a semiconductor device, the method comprising:
forming a set of contact placeholders over both a set of fins and a capping layer over the set of fins, the set of contact placeholders comprising nitride atop an oxide;
providing a dielectric layer over a set of gate structures formed over a substrate and over the set of contact placeholders;
patterning a set of source/drain (S/D) openings in the dielectric layer between the set of gate structures;
removing the nitride from atop the oxide;
removing the oxide selective to the dielectric layer and the capping layer;
forming a deep ultraviolet light absorbing oxide (DUO) fill over the set of gate structures, including within the set of S/D openings;
patterning a set of gate openings over the set of gate structures, wherein a portion of the dielectric layer directly adjacent the DUO fill formed within one of the set of S/D openings is removed, and at least one gate opening of the set of gate openings exposes on a bottom of the gate opening only a part or all of one gate structure of the set of gate structures;
removing the DUO fill selective to the dielectric layer; and
removing the capping layer from atop the set of gate structures within the set of gate openings and from atop a set of fins within the set of STD openings.
8. The method according to claim 7 , further comprising depositing a metal material over the semiconductor device to form a set of gate contacts within the set of gate openings and a set of S/D contacts within the set of S/D openings, wherein at least one of the set of gate contacts and at least one of the set of S/D contacts are merged.
9. The method according to claim 7 , the patterning the set of gate openings comprising partially etching the capping layer atop the set of gate structures within the set of gate openings.
10. The method according to claim 7 , the dielectric layer comprising silicon oxycarbide (SiOC), wherein the DUO is removed selective to the SiOC using an O2 plasma process.
11. The method according to claim 7 , wherein each of the set of gate openings has sloped sidewalls that converge towards the set of gate structures.