Self-aligned cross-point phase change memory-switch array
Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same.
1. A memory device comprising:
a plurality of memory structures, each of the plurality of memory structures comprising a phase change memory layer between a first memory electrode layer and a second memory electrode layer; and
a plurality of switch structures over the plurality of memory structures, each of the plurality of switch structures intersecting with at least two of the plurality of memory structures, and each of the plurality of switch structures comprising a phase change switch layer, a first switch electrode layer, and a second switch electrode layer, and wherein the phase change switch layer is between the first switch electrode layer and the second switch electrode layer, and the first switch electrode layer is in contact with the second memory electrode layer,
wherein the phase change switch layer extends to at least two memory cells of the memory device, and
wherein the first memory electrode layer, the phase change memory layer, the second memory electrode layer, and the first switch electrode layer are substantially localized at cross-points of the plurality of memory structures and the plurality of switch structures, and are isolated from immediately neighboring cross-points.
2. The memory device of claim 1 , wherein the plurality of switch structures and the plurality of memory structures are on horizontal levels between a first plurality of electrically conductive lines and a second plurality of electrically conductive lines, wherein the first plurality of electrically conductive lines and the second plurality of electrically conductive lines are configured to interconnect memory cells of the memory device.
3. The memory device of claim 2 , wherein the first plurality of electrically conductive lines is in contact with the plurality of memory structures and comprises a first plurality of metal lines, and wherein the second plurality of electrically conductive lines is in contact with the plurality of switch structures and comprises a second plurality of metal lines.
4. The memory device of claim 1 , wherein the second switch electrode layer extends to at least two memory cells of the memory device.
5. The memory device of claim 1 , wherein the first switch electrode layer and the second switch electrode layer comprise at least one of titanium nitride (TiN) and carbon.
6. The memory device of claim 1 , wherein the first plurality of conductive lines is in contact with the second switch electrode layer and the second plurality of conductive lines is in contact with the first memory electrode layer.
7. The memory device of claim 1 , wherein the first memory electrode layer and the second memory electrode layer comprise at least one of titanium nitride (TiN) and carbon.
8. A system comprising:
a memory device comprising a memory array, wherein the memory array comprises:
a plurality of memory structures in an array configuration, each of the plurality of memory structures comprising a phase change memory layer between a first memory electrode layer and a second memory electrode layer; and
a plurality of substantially parallel switch structures over the plurality of memory structures, each of the plurality of substantially parallel switch structures intersecting with at least two of the plurality of memory structures, and each of the plurality of substantially parallel switch structures comprising a phase change switch layer, a first switch electrode layer and a second switch electrode layer, and wherein the phase change switch layer is between the first switch electrode layer and the second switch electrode layer, and the first switch electrode layer is in contact with the second memory electrode layer,
wherein the phase change switch layer extends to at least two memory cells of the memory array, and
wherein the first memory electrode layer, the phase change memory layer, the second memory electrode layer, and the first switch electrode layer are substantially localized at cross-points of the plurality of memory structures and the plurality of substantially parallel switch structures, and are isolated from immediately neighboring cross-points;
a memory controller configured to access the memory array; and
a processor to host one or more applications and to initiate commands to the memory controller to provide access to the memory array.
9. The system of claim 8 , further comprising a first plurality of conductive lines and a second plurality of conductive lines, wherein the plurality of substantially parallel switch structures and the plurality of memory structures are on horizontal levels between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines.
10. The system of claim 9 , wherein the first electrically conductive lines and the second electrically conductive lines are configured to provide electrical communication between the memory controller and the memory array.
11. The system of claim 9 , wherein the first plurality of electrically conductive lines is in contact with the plurality of memory structures and comprises a first plurality of metal lines, and wherein the second plurality of electrically conductive lines is in contact with the plurality of substantially parallel switch structures and comprises a second plurality of metal lines.
12. The system of claim 8 , wherein the first memory electrode layer and the second memory electrode layer comprise at least one of titanium nitride (TiN) and carbon.
13. The system of claim 8 , wherein the second switch electrode layer extends to at least two memory cells of the memory array.
14. The system of claim 8 , wherein the first switch electrode layer and the second switch electrode layer comprise at least one of titanium nitride (TiN) and carbon.