Field effect transistors having multiple effective work functions
Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.
1. A semiconductor structure comprising:
a first gate dielectric straddling a first semiconductor material portion and containing a stack of an adjustment oxide layer including a silicate of a metal selected from alkaline earth metals, Group IIIB elements, and rare earth metals and a first high dielectric constant (high-k) gate dielectric including a dielectric metal oxide and having a dielectric constant greater than 8.0;
a first gate electrode in contact with said first gate dielectric and containing a first metallic material layer in contact with said first high-k gate dielectric;
a second gate dielectric straddling a second semiconductor material portion and containing a stack of a semiconductor oxide layer and a second high-k gate dielectric, wherein said first high-k gate dielectric differs in composition from said second high-k gate dielectric by presence of oxygen deficiency in said first high-k gate dielectric; and
a second gate electrode in contact with said second gate dielectric and containing a second metallic material layer in contact with said second high-k gate dielectric.
2. The semiconductor structure of claim 1 , wherein said second high-k gate dielectric does not include said metal in said silicate.
3. The semiconductor structure of claim 2 , wherein said first high-k gate dielectric includes said metal at a lesser concentration than said adjustment oxide layer.
4. The semiconductor structure of claim 1 , wherein said first metallic material layer and said second metallic material layer differ from each other in at least one of thickness and composition.
5. The semiconductor structure of claim 1 , further comprising a third gate dielectric straddling a semiconductor material stack and containing a stack of another adjustment oxide layer and a third high-k gate dielectric including said dielectric metal oxide, wherein said semiconductor material stack comprises a semiconductor shell structure embedding, having a different composition from, and in epitaxial alignment with, a third semiconductor material portion.
6. The semiconductor structure of claim 5 , further comprising a third gate electrode in contact with said third gate dielectric and containing a layer of a metallic material having a same composition and thickness as said first metallic material layer and in contact with said third high-k gate dielectric.
7. The semiconductor structure of claim 5 , further comprising a fourth gate dielectric straddling another semiconductor material stack and containing a stack of another semiconductor oxide layer and a fourth high-k gate dielectric having a same composition and thickness as said second high-k gate dielectric, wherein said another semiconductor material stack comprises another semiconductor shell structure embedding, having a different composition from, and in epitaxial alignment with, a fourth semiconductor material portion.
8. The semiconductor structure of claim 1 , wherein said first high-k gate dielectric and said second high-k gate dielectric include dielectric metal oxides of a same metal.
9. The semiconductor structure of claim 1 , wherein said first gate electrode further comprises another metallic material layer having a same composition and thickness as said second metallic material layer and in contact with said first metallic material layer.
10. The semiconductor structure of claim 1 , wherein each of said first and second gate electrodes further comprises a conductive material in contact with said another metallic material layer and said second metallic material layer, respectively.