Inductive load power switching circuits
Power switching circuits including an inductive load and a switching device are described. The switches devices can be either low-side or high-side switches. Some of the switches are transistors that are able to block voltages or prevent substantial current from flowing through the transistor when voltage is applied across the transistor.
1. A power-factor correction circuit, comprising:
a first switching device;
an inductive load;
a capacitor; and
a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel;
wherein the first switching device is connected to a node between the inductive load and the second switching device, and the second switching device is between the inductive load and the capacitor, and
wherein the power-factor correction circuit is configured such that
in a first mode of operation current flows through the channel of the depletion mode device in a first direction when the gate of the enhancement mode device is biased below a threshold voltage of the enhancement mode device,
in a second mode of operation current flows through the channel of the depletion mode device in the first direction when the gate of the enhancement mode device is biased above the threshold voltage of the enhancement mode device, and
in a third mode of operation the depletion mode device blocks voltage applied in a second direction across the switching device and the enhancement mode device blocks a voltage at least equal to an absolute value of a threshold voltage of the depletion mode device.
2. The power-factor correction circuit of claim 1 , wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
3. The power-factor correction circuit of claim 1 , wherein the depletion mode device is a high-voltage device, the enhancement mode device is a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
4. The power-factor correction circuit of claim 1 , wherein the depletion mode device comprises a III-N HEMT.
5. The power-factor correction circuit of claim 4 , wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
6. The power-factor correction circuit of claim 4 , wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
7. A power-factor correction circuit, comprising:
a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor;
a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor, wherein the first and second depletion mode transistors each comprise III-N HEMTs;
an inductive component; and
a capacitor;
wherein the inductive component, the first switching device and the second switching device are connected to a first node, and the second switching device and the capacitor are connected to a second node, and
wherein the power-factor correction circuit is configured such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
8. The power-factor correction circuit of claim 7 , wherein the first and second enhancement mode transistors each comprise Si MOS devices.
9. The power-factor correction circuit of claim 7 , wherein the power-factor correction circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
10. The power-factor correction circuit of claim 9 , wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
11. The power-factor correction circuit of claim 9 , wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor.
12. A method of forming a power-factor correction circuit, comprising:
providing a first switching device, an inductive load, a capacitor, and a second switching device, the second switching device comprising a depletion mode device and an enhancement mode device, the enhancement mode device including a gate, the depletion mode device including a channel;
connecting the first switching device to a node between the inductive load and the second switching device, wherein the second switching device is between the inductive load and the capacitor; and
configuring the power-factor correction circuit such that
in a first mode of operation current flows through the channel of the depletion mode device in a first direction when the gate of the enhancement mode device is biased below a threshold voltage of the enhancement mode device,
in a second mode of operation current flows through the channel of the depletion mode device in the first direction when the gate of the enhancement mode device is biased above the threshold voltage of the enhancement mode device, and
in a third mode of operation the depletion mode device blocks voltage applied in a second direction across the switching device and the enhancement mode device blocks a voltage at least equal to an absolute value of a threshold voltage of the depletion mode device.
13. The method of claim 12 , wherein in the third mode of operation the gate of the enhancement mode device is biased below the threshold voltage of the enhancement mode device.
14. The method of claim 12 , wherein the depletion mode device is provided as a high-voltage device, the enhancement mode device is provided as a low-voltage device, and the second switching device is configured to operate as a high-voltage enhancement mode device.
15. The method of claim 12 , wherein the depletion mode device comprises a III-N HEMT.
16. The method of claim 15 , wherein the enhancement mode device comprises a Si MOS device or a III-N HEMT.
17. The method of claim 15 , wherein the enhancement mode device comprises a Si MOS device, the Si MOS device includes an inherent parasitic diode, and the switching device further comprises a Schottky diode connected antiparallel to the Si MOS device.
18. A method of forming a power-factor correction circuit, comprising:
providing a first switching device comprising a first depletion mode transistor and a first enhancement mode transistor;
providing a second switching device comprising a second depletion mode transistor and a second enhancement mode transistor, wherein the first and second depletion mode transistors each comprise III-N HEMTs;
providing an inductive component;
providing a capacitor;
connecting the inductive component, the first switching device and the second switching device to a first node, and connecting the second switching device and the capacitor to a second node; and
configuring the power-factor correction circuit such that in a first mode of operation current flows through a channel of the second depletion mode transistor in a first direction when a gate of the second enhancement mode transistor is biased below a threshold voltage of the second enhancement mode transistor, and in a second mode of operation current flows through the channel of the second depletion mode transistor in the first direction when the gate of the second enhancement mode transistor is biased above the threshold voltage of the second enhancement mode transistor.
19. The method of claim 18 , wherein the first and second enhancement mode transistors each comprise Si MOS devices.
20. The method of claim 18 , wherein the power-factor correction circuit is configured such that in a third mode of operation the second depletion mode transistor blocks voltage applied in a second direction across the second switching device.
21. The method of claim 20 , wherein in the third mode of operation the second enhancement mode transistor blocks a voltage at least equal to an absolute value of a threshold voltage of the second depletion mode transistor.
22. The method of claim 20 , wherein in the third mode of operation the gate of the second enhancement mode transistor is biased below the threshold voltage of the second enhancement mode transistor.