High Voltage Semiconductor Devices and Methods for their Fabrication
Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described.
1 . A semiconductor device comprising:
a semiconductor substrate in which a source region and a drain region are disposed;
a gate structure supported by the semiconductor substrate between the source region and the drain region;
a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region comprising dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and
a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device.
2 . The semiconductor device of claim 1 wherein the composite drift region comprises a first lateral section adjacent to the drain region and a second lateral section adjacent to the well section, and wherein a lower boundary of the first lateral section is deeper in the semiconductor substrate than a lower boundary of the second lateral section.
3 . The semiconductor device of claim 1 wherein the dopant comprises a plurality of different types of atoms.
4 . The semiconductor device of claim 1 wherein at least a portion of the dopant is buried at a depth greater than 1 micron beneath a top surface of the semiconductor substrate.
5 . The semiconductor device of claim 1 wherein at least a portion of the dopant is buried at a depth greater than 2 microns beneath a top surface of the semiconductor substrate.
6 . The semiconductor device of claim 1 wherein at least a portion of the dopant is buried at a depth greater than 2.5 microns beneath a top surface of the semiconductor substrate.
7 . The semiconductor device of claim 1 wherein the dopant comprises one or a plurality of different types of n-type dopant.
8 . The semiconductor device of claim 7 wherein the dopant is selected from the group consisting of arsenic (As), phosphorus (P), and a combination thereof.
9 . The semiconductor device of claim 1 wherein at least a portion of the buried dopant is provided in at least one of a plurality of epitaxial layers in the semiconductor substrate.
10 . The semiconductor device of claim 9 wherein the plurality of epitaxial layers comprises a first epitaxial layer having a thickness of at least 15 microns, and a second epitaxial layer overlaying the first epitaxial layer and having a thickness of between 2 microns and 3 microns.
11 . The semiconductor device of claim 10 wherein the composite drift region comprises a shallow region and a buried region, and wherein the shallow region is electrically coupled with the buried region.
12 . An electronic apparatus comprising:
a substrate; and
a field-effect transistor device disposed in the substrate, the field-effect transistor device comprising:
first and second semiconductor regions having a first conductivity type and configured for application of a voltage therebetween during operation of the field-effect transistor device;
a third semiconductor region having a second conductivity type and configured to form a channel therein between the first semiconductor region and the second semiconductor region during operation of the field-effect transistor device; and
a fourth semiconductor region extending laterally from the first semiconductor region towards the third semiconductor region, the fourth semiconductor region comprising dopant having the first conductivity type, wherein at least a portion of the dopant is buried beneath the first semiconductor region at a depth exceeding an ion implantation range.
13 . The electronic apparatus of claim 12 wherein at least a portion of the dopant is buried at a depth greater than 2 microns.
14 . The electronic apparatus of claim 12 wherein the dopant comprises an n-type dopant.
15 . The electronic apparatus of claim 12 wherein at least a portion of the buried dopant is provided in at least one of a plurality of epitaxial layers in the field-effect transistor device.
16 . The electronic apparatus of claim 15 wherein the plurality of epitaxial layers comprises a first epitaxial layer having a thickness of at least 15 microns, and a second epitaxial layer overlaying the first epitaxial layer and having a thickness of between 2 microns and 3 microns.
17 . The electronic apparatus of claim 16 wherein the fourth semiconductor region comprises a shallow region of the first conductivity type and a buried region of the first conductivity type, and wherein the shallow region is electrically coupled with the buried region.
18 . A method of fabricating a semiconductor device, the method comprising:
forming a source region and a drain region in a semiconductor substrate;
forming a well region in the semiconductor substrate, the well region configured to form a channel during operation of the semiconductor device;
forming a gate structure between the source region and the drain region; and
forming a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region comprising dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range.
19 . The method of claim 19 wherein the forming of the composite drift region comprises:
forming a first epitaxial layer;
masking at least a portion of the first epitaxial layer;
implanting a dopant having the first conductivity type in at least an unmasked portion of the first epitaxial layer, at least a portion of the unmasked portion being substantially aligned with the drain region;
forming a second epitaxial layer over the first epitaxial layer; and
implanting a dopant having the first conductivity type in the second epitaxial layer.
20 . The method of claim 19 wherein the dopant implanted in the first epitaxial layer and the dopant implanted in the second epitaxial layer are each independently selected from the group consisting of arsenic (As), phosphorus (P), and a combination thereof.