Granted Patent B2

US 9,029,824 · App. 14/449,044 · Granted May 12, 2015

Abstract

Claims (22)

1. A memory device comprising:

a plurality of memory arrays formed along a first direction, each of said memory arrays including:

a memory region comprising an array of memory cells arranged in an array with a pitch of 2 F in a second direction substantially perpendicular to said first direction; and

a first and a second stitch region disposed adjacent said memory region along said first direction having a first and second row of gate contacts disposed therein, respectively, said first and second row of gate contacts being arranged along said second direction with a pitch of 4 F, each of said first and second row of gate contacts being connected to a respective row of said memory cells along said first direction; and

a first and second plurality of word lines extending along said first direction,

wherein each row of said first and second row of gate contacts of each of said memory arrays are coupled to said first or second plurality of word lines.

2. A memory device comprising:

a semiconductor substrate having a plurality of parallel trenches therein extending along a first direction, each of said trenches having a respective pair of a plurality of paired trench sidewalls;

a memory region formed in said semiconductor substrate, said memory region including an array of memory cells;

a plurality of paired gate electrodes formed on said paired trench sidewalls, said gate electrodes coupled to said memory cells along said first direction; and

a first and a second stitch region disposed adjacent said memory region along said first direction including a first and a second row of gate contacts, respectively, formed in said trenches along a second direction substantially orthogonal to said first direction,

wherein one of each pair of said gate electrodes is coupled to a respective one of said first row of gate contacts disposed in a respective one of said trenches and the other one of each pair of said gate electrodes is coupled to a respective one of said second row of gate contacts disposed in said respective one of said trenches.

3. The memory device according to claim 2 , wherein each of said trenches has a respective one of said first row of gate contacts and a respective one of said second row of gate contacts disposed therein.

4. The memory device according to claim 2 , wherein said semiconductor substrate comprises silicon.

5. The memory device according to claim 2 , wherein said semiconductor substrate has a p-type conductivity.

6. The memory device according to claim 2 , wherein said buried source electrodes have an n-type conductivity.

7. The memory device according to claim 2 , wherein said memory cells in said memory region are arranged in a square array with a pitch of 2 F in said first and said second direction.

8. The memory device according to claim 2 , wherein said first row of gate contacts and said second row of gate contacts are arranged to have a pitch of 4 F in said second direction.

9. The memory device according to claim 2 , further comprising:

a first and a second plurality of substrates contacts coupled to said substrate in said first and said second stitch region, respectively; and

a plurality of parallel substrate lines coupled to said first and said second plurality of substrate contacts along said second direction.

10. The memory device according to claim 9 , wherein said first and said second plurality of substrate contacts are disposed on top of trench sidewall regions where said gate electrodes have been severed.

Assignments (7)