Methods of forming alternative channel materials on FinFET semiconductor devices
One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.
1. A method, comprising:
forming an initial fin structure in a semiconductor substrate;
forming a layer of insulating material around said initial fin structure;
performing a recess etching process to recess said initial fin structure and thereby define a recessed fin structure and a replacement fin cavity in said layer of insulating material above said recessed fin structure;
forming at least first and second individual layers of epi semiconductor material in said replacement fin cavity, wherein each of said first and second layers have different concentrations of germanium;
performing an anneal process on said first and second layers so as to form a substantially homogeneous SiGe replacement fin in said fin cavity;
recessing said layer of insulating material so as to thereby expose at least an upper portion of said replacement fin; and
forming a gate structure around at least a portion of said replacement fin exposed above said recessed layer of insulating material.
2. The method of claim 1 , wherein said first layer is formed on said recessed fin structure and said second layer is formed on said first layer.
3. The method of claim 1 , wherein said first and second layers substantially fill said replacement fin cavity.
4. The method of claim 1 , further comprising forming third and fourth individual layers of epi semiconductor material in said replacement fin cavity above said second layer, wherein said third and fourth layers have different concentrations of germanium.
5. The method of claim 1 , wherein said recessed fin structure is made of silicon, said first layer is made of epi silicon germanium (Si (1−x) Ge x ), where “x” is greater than zero but less than 1, and said second layer is made of epi silicon.
6. The method of claim 1 , wherein said recessed fin structure is made of silicon, said first layer is made of epi silicon germanium (Si (1−x) Ge x ), where “x” is greater than zero but less than 1, and said second layer is made of epi silicon germanium (Si (1−x) Ge x ), where “x” is greater than zero but less than 1.
7. The method of claim 1 , wherein said recessed fin structure is made of silicon, said first layer is made of substantially pure epi germanium (Ge) and said second layer is made of epi silicon germanium (Si (1−x) Ge x ), where “x” is greater than zero but less than 1.
8. The method of claim 1 , wherein, after performing said anneal process, a germanium concentration in said substantially homogeneous SiGe replacement fin is intermediate said different concentrations of germanium in said first and second layers.
9. The method of claim 1 , wherein said first and second layers are formed to the same thickness.
10. The method of claim 1 , wherein said first and second layers are formed to different thicknesses.
11. The method of claim 1 , wherein performing said anneal process comprises performing a mixing thermal anneal process at a temperature that falls within the range of 700-1100° C.
12. The method of claim 1 , wherein performing said anneal process comprises performing a condensation anneal process in an oxidizing process ambient at a temperature that falls within the range of 500-1100° C.
13. The method of claim 1 , where one of said first and second layers is substantially pure germanium or substantially pure silicon.
14. The method of claim 1 , wherein said substantially homogeneous SiGe replacement fin is substantially defect-free.
15. The method of claim 1 , wherein each of said at least first and second individual layers of epi semiconductor material are formed to a thickness that is less than a critical thickness for such epi semiconductor material.
16. A method, comprising:
forming an initial fin structure in a silicon substrate;
forming a layer of insulating material around said initial fin structure;
performing a recess etching process to recess said initial fin structure and thereby define a recessed fin structure and a replacement fin cavity in said layer of insulating material above said recessed fin structure;
forming at least first and second individual layers of epi SiGe semiconductor material in said replacement fin cavity, wherein each of said first and second layers have different concentrations of germanium;
performing a mixing thermal anneal process at a temperature that falls within the range of 700-1100° C. on said first and second layers so as to form a substantially homogeneous SiGe replacement fin in said fin cavity;
recessing said layer of insulating material so as to thereby expose at least an upper portion of said replacement fin; and
forming a gate structure around at least a portion of said replacement fin exposed above said recessed layer of insulating material.
17. The method of claim 16 , further comprising forming third and fourth individual layers of epi semiconductor material in said replacement fin cavity above said second layer, wherein said third and fourth layers have different concentrations of germanium.
18. The method of claim 16 , wherein, after performing said anneal process, a germanium concentration in said substantially homogeneous SiGe replacement fin is intermediate said different concentrations of germanium in said first and second layers.
19. The method of claim 16 , wherein said substantially homogeneous SiGe replacement fin is substantially defect-free.
20. The method of claim 16 , wherein each of said at least first and second individual layers of epi SiGe semiconductor material are formed to a thickness that is less than a critical thickness for such epi SiGe semiconductor material.
21. A method, comprising:
forming an initial fin structure in a silicon substrate;
forming a layer of insulating material around said initial fin structure;
performing a recess etching process to recess said initial fin structure and thereby define a recessed fin structure and a replacement fin cavity in said layer of insulating material above said recessed fin structure;
forming at least first and second individual layers of epi SiGe semiconductor material in said replacement fin cavity, wherein each of said first and second layers have different concentrations of germanium;
performing a condensation anneal process in an oxidizing process ambient at a temperature that falls within the range of 500-1100° C. on said first and second layers so as to form a substantially homogeneous SiGe replacement fin in said fin cavity;
recessing said layer of insulating material so as to thereby expose at least an upper portion of said replacement fin; and
forming a gate structure around at least a portion of said replacement fin exposed above said recessed layer of insulating material.
22. The method of claim 21 , further comprising forming third and fourth individual layers of epi semiconductor material in said replacement fin cavity above said second layer, wherein said third and fourth layers have different concentrations of germanium.
23. The method of claim 21 , wherein, after performing said anneal process, a germanium concentration in said substantially homogeneous SiGe replacement fin is intermediate said different concentrations of germanium in said first and second layers.
24. The method of claim 21 , wherein said substantially homogeneous SiGe replacement fin is substantially defect-free.
25. The method of claim 21 , wherein each of said at least first and second individual layers of epi SiGe semiconductor material are formed to a thickness that is less than a critical thickness for such epi SiGe semiconductor material.