Package configurations for low EMI circuits
An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
1. A method of forming an assembly, comprising:
providing a first transistor comprising a first source, the first transistor encased in a first package, the first package comprising a first conductive structural portion, and
providing a second transistor comprising a second source and a second drain, the second transistor encased in a second package, the second package comprising a second conductive structural portion, wherein
the first source is electrically connected to the first conductive structural portion, the second source is electrically isolated from the second conductive structural portion, and the second drain is electrically isolated from the second conductive structural portion.
2. The method of claim 1 , wherein the first transistor or the second transistor is a high voltage switching transistor.
3. The method of claim 1 , wherein the first conductive structural portion or the second conductive structural portion is mounted directly on a heat sink and is electrically connected to the heat sink.
4. The method of claim 1 , wherein the first conductive structural portion or the second conductive structural portion is electrically connected to a circuit ground.
5. The method of claim 1 , wherein a drain of the first transistor is electrically connected to a source of the second transistor.
6. The method of claim 5 , wherein the first transistor is provided as a low-side switch and the second transistor is provided as a high-side switch.
7. The method of claim 1 , wherein the assembly is part of a half bridge.
8. The method of claim 1 , wherein the first transistor or the second transistor is provided as a III-N transistor.
9. The method of claim 1 , wherein the first transistor or the second transistor is provided as a lateral device.
10. A method of forming an assembly, comprising:
providing a first transistor comprising a first source and a first drain, the first transistor encased in a first package; and
providing a second transistor comprising a second source and a second drain, the second transistor encased in a second package; wherein
the first package comprises a first conductive structural portion and a first drain lead;
the second package comprises a second conductive structural portion and a second source lead;
the first source is electrically connected to the first conductive structural portion;
the second source is electrically isolated from the second conductive structural portion; and
the first drain lead is electrically connected to the second source lead.
11. The method of claim 10 , wherein the first conductive structural portion or the second conductive structural portion is electrically connected to a circuit ground.
12. The method of claim 10 , wherein the first transistor or the second transistor is provided as a lateral device.
13. The method of claim 10 , wherein the first transistor or the second transistor is provided as a III-N transistor.
14. The method of claim 10 , the first package further comprising a first source lead and a first gate lead, wherein the first source lead is between the first gate lead and the first drain lead.
15. The method of claim 14 , the first package further comprising a case, the case comprising the first conductive structural portion and a first insulating portion, wherein the gate lead, the source lead, and the drain lead each extend from the first insulating portion.
16. A method of forming an assembly, comprising:
providing a first transistor comprising a semiconductor layer, a first source, and a first drain, the first transistor encased in a first package; and
providing a second transistor comprising a second source and a second drain, the second transistor encased in a second package; wherein
the first package comprises a first conductive structural portion, a first source lead, a first gate lead, and a first drain lead, the first source lead being between the first gate lead and the first drain lead;
the first source and the first drain are each on an opposite side of the semiconductor layer from the first conductive structural portion;
the second package comprises a second conductive structural portion; and
the second source is electrically isolated from the second conductive structural portion.
17. The method of claim 16 , wherein the first source is electrically connected to the first conductive structural portion.
18. The method of claim 16 , the second package further comprising a second source lead, wherein the first drain lead is electrically connected to the second source lead.
19. The method of claim 16 , wherein the first transistor or the second transistor is provided as a III-N transistor.
20. The method of claim 16 , wherein the second drain is electrically isolated from the second conductive structural portion.
21. A method of forming an assembly, comprising:
providing a first transistor comprising a first source, the first transistor encased in a first package, the first package comprising a first conductive structural portion; and
providing a second transistor comprising a second source and encased in a second package, the second package comprising a second conductive structural portion and three leads; wherein
the first source is electrically connected to the first conductive structural portion, the second source is electrically isolated from the second conductive structural portion, and the three leads are each electrically isolated from the second conductive structural portion.
22. The method of claim 21 , wherein the first transistor or the second transistor is provided as a lateral device.
23. The method of claim 21 , wherein the first transistor or the second transistor is provided as a III-N transistor.
24. A method of forming an assembly, comprising:
providing a first transistor encased in a first package, the first package comprising a first conductive structural portion, the first transistor comprising a source, a gate, a drain, and a semiconductor layer, wherein the source, the gate, and the drain are all on a first side of the semiconductor layer; and
providing a second transistor encased in a second package, the second package comprising a second conductive structural portion; wherein
the source of the first transistor is electrically connected to the first conductive structural portion and a drain of the second transistor is electrically connected to the second conductive structural portion.
25. The method of claim 24 , wherein the first transistor or the second transistor is provided as a high voltage switching transistor.
26. The method of claim 24 , wherein the first transistor or the second transistor is provided as a III-N transistor.
27. The method of claim 24 , wherein the first conductive structural portion is electrically connected to a circuit ground or to a DC ground.
28. The method of claim 27 , wherein the second conductive structural portion is electrically connected to a DC high voltage supply.
29. The method of claim 28 , wherein the second conductive structural portion is separated from the circuit ground or the DC ground by an insulating spacer.
30. The method of claim 29 , wherein a capacitance between the second conductive structural portion and the circuit ground or DC ground causes the second conductive structural portion to be AC grounded.
31. The method of claim 24 , wherein the drain of the first transistor is electrically connected to a source of the second transistor.
32. The method of claim 24 , wherein the first transistor is provided as a low-side switch and the second transistor is provided as a high-side switch.