IP Library Granted Patent US 9,659,993
Granted Patent B2
US 9,659,993 · App. 14/482,650 · Granted May 23, 2017

Vertical integration of CMOS electronics with photonic devices

Inventors: John Dallesasse (Geneva, IL); Stephen B. Krasulick (Albuquerque, NM); Timothy Creazzo (Albuquerque, NM); Elton Marchena (Albuquerque, NM)
Assignee: Skorpios Technologies, Inc.
H01L27/14689H01L21/76254H01L21/8258H01L21/84H01L27/0688H01L27/12H01L27/14625H01L27/14634H01L27/14643H01L27/14687H01L27/15H01L21/8221
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Quick Facts
Patent No.
US 9,659,993
App. No.
14/482,650
Granted
May 23, 2017
Kind
B2
Abstract

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

Claims (26)

1. A method of fabricating a composite semiconductor structure, the method comprising:

providing a substrate;

providing a photonic die, the photonic die comprising III-V material;

aligning the photonic die with the substrate;

joining the substrate and the photonic die to form a composite substrate; and

processing the composite substrate to form a feature on the photonic die, wherein:

the processing the composite substrate is performed after joining the substrate and the photonic die;

the feature on the photonic die is a stripe region; and

the stripe region is an optical waveguide.

2. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the processing the composite substrate further includes forming an electrical interconnect on the photonic die.

3. The method of fabricating the composite semiconductor structure as recited in claim 1 , further comprising using an alignment tolerance of approximately ±10 μm for aligning the photonic die with the substrate.

4. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the processing the composite substrate further forms an optical waveguide on the substrate.

5. The method of fabricating the composite semiconductor structure as recited in claim 1 , the method further comprising growing epitaxial layers on the photonic die after joining the substrate and the photonic die to form the composite substrate.

6. The method of fabricating the composite semiconductor structure as recited in claim 1 , the method further comprising:

providing an assembly substrate having a base layer and a device layer;

mounting the photonic die on a predetermined portion of the assembly substrate;

aligning the assembly substrate with the substrate to align the photonic die with the substrate; and

removing at least the base layer of the assembly substrate from the composite substrate after the photonic die and the substrate are joined.

7. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein:

the photonic die is a first photonic die; and

the method further comprises:

providing a second photonic die;

mounting the first photonic die and the second photonic die on an assembly substrate; and

aligning the assembly substrate with the substrate.

8. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

9. The method of fabricating the composite semiconductor structure as recited in claim 1 , wherein the substrate comprises silicon-based devices.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Nov 22, 2017
From: PACIFIC WESTERN BANK
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 044751/0469 →
SECURITY INTEREST Recorded Oct 23, 2017
From: SKORPIOS TECHNOLOGIES, INC.
To: PACIFIC WESTERN BANK
Reel/Frame 044272/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2014
From: DALLESASSE, JOHN; KRASULICK, STEPHEN B.; CREAZZO, TIMOTHY; MARCHENA, ELTON
To: SKORPIOS TECHNOLOGIES, INC.
Reel/Frame 033987/0736 →
Continuity (3)
Continuation 13745577 · Jan 18, 2013
Provisional Application 61588080 · Jan 18, 2012
Related Publication 20150123157A1 · May 7, 2015