Efficient wide range bit counter
An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.
1. An event counter circuit formed on an integrated circuit, comprising:
a first counter having a first capacity connected to count a number of occurrences of a first sub-set of a first event;
a second counter having a second capacity connected to count a number of occurrences of a second sub-set of the first event; and
logic circuitry connected to the first and second counters,
wherein the logic circuitry provides the count of the number of occurrences of the first event as a sum of values of the first and second counters when neither of the first counter or the second counter has reached a respective capacity, and
in response to a first one of the first and second counters reaching its respective capacity, the other of the first and second counters is used as an extension of the first one of the first and second counters, wherein the logic circuitry provides the count of the number of occurrences of the first event as the values of the first one of the first and second counters scaled according to the counters' relative capacities.
2. The event counter circuit of claim 1 , wherein the first and second counters have the same capacity, and wherein in response to providing the count of the number of occurrences of the first event as the values of the first one of the first and second counters scaled according to the counters' relative capacities, the logic circuitry doubles the count of the first one of the first and second counters.
3. The event counter circuit of claim 1 , wherein the integrated circuit comprises a non-volatile memory circuit.
4. The event counter circuit of claim 3 , wherein the first event is a data error.
5. The event counter circuit of claim 3 , wherein the first event is a programming cycle in a write operation.
6. The event counter circuit of claim 3 , wherein the count of the number of occurrences of the first event is used to determine whether to terminate a write operation.
7. The event counter circuit of claim 3 , wherein the count of the number of occurrences of the first event is used to determine whether to terminate a program verify operation.
8. The event counter circuit of claim 3 , wherein the count of the number of occurrences of the first event is used to determine data states to verify during a write operation.
9. The event counter circuit of claim 3 , wherein the count of the number of occurrences of the first event is used to determine whether the non-volatile memory circuit has a defect.
10. The event counter circuit of claim 3 , wherein the non-volatile memory circuit is formed according to a NAND type of architecture.
11. The event counter circuit of claim 3 , wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device comprising: memory cells arranged in multiple physical levels above a silicon substrate; and
a charge storage medium.
12. The event counter circuit of claim 3 , wherein the first and second sub-sets of the first event correspond to occurrences of the first event in distinct physical elements of an array of memory cells of the non-volatile memory circuit.
13. The event counter circuit of claim 1 , wherein the count of the number of occurrences of the first event is counted sequentially as a series of partial counts and wherein, in response to the count of the number of occurrences of the first event being terminated prior to completing the series of partial counts, the logic circuitry provides an approximated value of the count of the number of occurrences of the first event for a complete series of partial counts.
14. The event counter circuit of claim 13 , wherein the logic circuitry generates the approximated values of the count of the number of occurrences of the first event from completed ones of the series of partial counts by a combination of a multiplication operation and a shift operation performed on a sum of the series of partial counts.
15. The event counter circuit of claim 1 , wherein the logic circuitry provides the count of the number of occurrences of the first event in a format of a significand times two to the power of an exponent.
16. The event counter circuit of claim 15 , wherein the logic circuitry scales the count of the number of occurrences of the first event by increasing the value of the exponent.