Mapping of random defects in a memory device
View Patent ↗A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.
1. A method of managing random defects in a memory device comprising:
receiving an incoming address identifying a memory location to be accessed in a memory array of the memory device, the memory array being made of a plurality of memory cells, the incoming address including a row address and a column address, a row address and a column address identifying a memory location of a memory cell of the memory array, the column address belonging to a group of column addresses that are associated with a plurality of row addresses, each of the associated plurality of row addresses of a group of column addresses identifying no more than one defective memory cell;
determining whether or not the incoming address identifies a defective memory cell; and
if the incoming column address identifies a defective memory cell, identifying an alternate column address;
for each group of column addresses, identifying a defective column address using the incoming row address;
comparing the incoming column address to the defective column address of each group; and
if a match is found between the incoming column address and the defective column address of any of the groups, replacing the incoming column address with the alternate column address to be used for identifying an alternate memory location in the memory array;
determining whether or not the incoming row address is associated with a defective memory cell; and
if it is determined that the incoming row address is associated with a defective memory cell, replacing the incoming row address with an alternate row address for identifying the alternate memory location in the memory device.
2. The method of managing, as recited in claim 1 , further comprising determining that the memory cell is not defective using a predetermined value.
3. The method of managing, as recited in claim 1 , further comprising determining that the memory cell is not defective using a flag.
4. The method of managing, as recited in claim 1 , wherein if it is determined that there is no match between the incoming column address and the defective column address, using the incoming column address for identifying the memory location to be accessed.
5. The method of managing, as recited in claim 1 , wherein if it is determined that there is no match between the incoming row address and the defective row address, using the incoming row address for identifying the memory location to be accessed.
6. The method of managing, as recited in claim 1 , wherein the plurality of memory cells of the memory device are random access memory (RAM) cells.
7. The method of managing, as recited in claim 1 , wherein the plurality of memory cells of the memory device are magnetic random access memory (MRAM) cells.
8. The method of managing, as recited in claim 1 , further comprising using a content addressable memory (CAM) for the step of determining whether or not the incoming column address is associated with a defective memory cell.