IP Library Granted Patent US 9,589,860
Granted Patent B2
US 9,589,860 · App. 14/508,645 · Granted Mar 7, 2017

Electronic devices with semiconductor die coupled to a thermally conductive substrate

Inventors: Lakshminarayan Viswanathan (Phoenix, AZ); Jaynal A. Molla (Gilbert, AZ)
Assignee: NXP USA, INC.
H01L23/3114H01L21/6835H01L21/6836H01L23/36H01L23/3677H01L23/4827H01L23/66H01L24/03H01L24/05H01L24/27H01L24/29H01L24/741H01L24/743H01L24/92H01L24/94H01L21/561H01L23/49513H01L23/49517H01L24/32H01L24/48H01L24/83H01L2221/6834H01L2221/68318H01L2221/68327H01L2221/68381H01L2224/0332H01L2224/0345H01L2224/0346H01L2224/03312H01L2224/03436H01L2224/03505H01L2224/04026H01L2224/05009H01L2224/05018H01L2224/05073H01L2224/05082H01L2224/0589H01L2224/05124H01L2224/05139H01L2224/05144H01L2224/05147H01L2224/05166H01L2224/05551H01L2224/05558H01L2224/05559H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05647H01L2224/05666H01L2224/05794H01L2224/05839H01L2224/05844H01L2224/05847H01L2224/05855H01L2224/05864H01L2224/05887H01L2224/05893H01L2224/2731H01L2224/2732H01L2224/27312H01L2224/27436H01L2224/27438H01L2224/27505H01L2224/291H01L2224/293H01L2224/29006H01L2224/2908H01L2224/29011H01L2224/2912H01L2224/29012H01L2224/29017H01L2224/2918H01L2224/2919H01L2224/2929H01L2224/2939H01L2224/29082H01L2224/29083H01L2224/29084H01L2224/29101H01L2224/29109H01L2224/29111H01L2224/29113H01L2224/29116H01L2224/29117H01L2224/29118H01L2224/29124H01L2224/29138H01L2224/29139H01L2224/29144H01L2224/29147H01L2224/29184H01L2224/29193H01L2224/29294H01L2224/29339H01L2224/29344H01L2224/29347H01L2224/29355H01L2224/29364H01L2224/29387H01L2224/29393H01L2224/32245H01L2224/48247H01L2224/73265H01L2224/741H01L2224/8346H01L2224/83191H01L2224/83193H01L2224/83444H01L2224/83447H01L2224/83455H01L2224/83815H01L2224/92H01L2224/92247H01L2224/94H01L2924/00014H01L2924/1033H01L2924/10158H01L2924/10253H01L2924/10272H01L2924/1421
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,589,860
App. No.
14/508,645
Granted
Mar 7, 2017
Kind
B2
Abstract

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Claims (43)

1. An electronic device comprising:

a thermally conductive substrate;

a work piece that includes

a semiconductor die having a plurality of major surfaces including an upper surface and a lower surface, and

a sintered metallic layer applied to the lower surface of the semiconductor die; and

a thermally conductive flow layer between a lower surface of the sintered metallic layer and the thermally conductive substrate, wherein the thermally conductive flow layer couples the work piece to the thermally conductive substrate.

2. The electronic device of claim 1 , wherein the semiconductor die is selected from gallium nitride and silicon.

3. The electronic device of claim 1 , wherein the semiconductor die comprises silicon.

4. The electronic device of claim 1 , wherein the semiconductor die comprises radio frequency circuitry.

5. The electronic device of claim 1 , wherein the semiconductor die has a thickness in a range of 10 μm to 50 μm.

6. The electronic device of claim 1 , wherein the sintered metallic layer includes silver, gold, palladium, copper, nickel, or any combination thereof.

7. The electronic device of claim 1 , wherein the sintered metallic layer has a thickness in a range of 10 μm to 200 μm.

8. The electronic device of claim 1 , wherein the sintered metallic layer has a modulus in a range of 5 GPa to 25 GPa.

9. The electronic device of claim 1 , wherein the sintered metallic layer has a density in a range of 40% to 95%.

10. The electronic device of claim 1 , wherein the semiconductor die includes a set of vias including metal.

11. The electronic device of claim 10 , wherein the sintered metallic layer is in direct contact with the metal of the vias.

12. The electronic device of claim 1 , wherein the sintered metallic layer is in direct contact with the conductive flow layer.

13. The electronic device of claim 1 , wherein conductive flow layer includes a solder.

14. The electronic device of claim 13 , wherein the solder has a melting point in a range of 150° C. to 380° C.

15. The electronic device of claim 1 , wherein the conductive flow layer has a thickness in a range of 10 μm to 50 μm.

16. The electronic device of claim 1 , wherein the substrate includes a lead frame.

17. The electronic device of claim 16 , wherein the lead frame is a copper lead frame.

18. The electronic device of claim 1 , further comprising an interposer disposed between the sintered metallic layer and the thermally conductive flow layer.

19. The electronic device of claim 1 , wherein the sintered metallic layer is applied fully to the lower surface of the semiconductor die.

20. The electronic device of claim 1 , wherein the sintered metallic layer is applied in a pattern to the lower surface of the semiconductor die.

21. The electronic device of claim 1 , wherein the sintered metallic layer includes silver.

22. The electronic device of claim 1 , wherein the thermally conductive flow layer underlies a full lower surface of the sintered metallic layer.

23. The electronic device of claim 1 , wherein the thermally conductive flow layer includes silver.

24. An electronic device comprising:

a thermally conductive substrate;

a semiconductor die disposed over the thermally conductive substrate and having a plurality of major surfaces including an upper surface and a lower surface;

a sintered metallic layer disposed between the lower surface of the semiconductor die and the thermally conductive substrate; and

a thermally conductive, silver-containing layer between a lower surface of the sintered metallic layer and the thermally conductive substrate, wherein the thermally conductive, silver-containing layer couples the sintered metallic layer and the semiconductor die to the thermally conductive substrate.

25. The electronic device of claim 24 , wherein the semiconductor die is selected from gallium nitride and silicon.

26. The electronic device of claim 24 , wherein the semiconductor die has a thickness in a range of 10 μm to 50 μm.

27. The electronic device of claim 24 , wherein the sintered metallic layer includes silver, gold, palladium, copper, nickel, or any combination thereof.

28. The electronic device of claim 24 , wherein the sintered metallic layer is a sintered silver layer.

29. The electronic device of claim 24 , wherein the sintered metallic layer has a thickness in a range of 10 μm to 200 μm.

30. The electronic device of claim 24 , wherein the semiconductor die includes a set of vias including metal.

31. The electronic device of claim 30 , wherein the sintered metallic layer is in direct contact with the metal of the vias.

32. The electronic device of claim 24 , wherein the sintered metallic layer is in direct contact with the conductive silver-containing layer.

33. The electronic device of claim 24 , wherein the thermally conductive, silver-containing layer has a thickness in a range of 10 μm to 50 μm.

34. The electronic device of claim 24 , wherein the thermally conductive, silver-containing layer underlies a full lower surface of the sintered metallic layer.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2014
From: VISWANATHAN, LAKSHMINARAYAN; MOLLA, JAYNAL A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033904/0996 →
Continuity (1)
Related Publication 20160099199A1 · Apr 7, 2016