Method of forming stressed semiconductor layer

1. A method of forming a semiconductor layer, the method comprising:

forming, in a semiconductor structure including a stressed semiconductor layer, one or more first isolation trenches in a first direction delimiting a first dimension of at least one transistor to be formed in said semiconductor structure;

forming, in said semiconductor structure, one or more second isolation trenches in a second direction delimiting a second dimension of said at least one transistor, said one or more first and second isolation trenches being at least partially filled with an insulating material having a viscosity; and

before or after forming said one or more second isolation trenches, decreasing the viscosity of the insulating material in said one or more first isolation trenches by implanting atoms of a first material into said one or more first isolation trenches, wherein atoms of said first material are not implanted into said one or more second isolation trenches.

2. The method of claim 1 , wherein said first material is boron or phosphor.

3. The method of claim 1 , wherein said semiconductor structure further comprises a layer overlying said stressed semiconductor layer, the method further comprising:

after implanting atoms, removing said layer.

4. The method of claim 1 , wherein:

each of said at least one transistor is a p-channel MOS transistor, and wherein said first dimension is a width of said at least one transistor; or

each of said at least one transistor is an n-channel MOS transistor, and wherein said first dimension is a length of said at least one transistor.

5. The method of claim 1 , further comprising, prior to implanting atoms, forming, in said semiconductor structure, at least two third trenches in said second direction delimiting said second dimension of at least one second transistor to be formed in said semiconductor structure, wherein:

the at least one transistor is a plurality of transistors;

a first transistor of the plurality of transistors is a p-channel MOS transistor and said first dimension is a width of said first transistor; and

a second transistor of the plurality of transistors is an n-channel MOS transistor and said second dimension is a length of said second transistor.

6. The method of claim 1 , wherein said stressed semiconductor layer is part of a bulk semiconductor layer.

7. The method of claim 1 , wherein said stressed semiconductor layer comprises a plurality of semiconductor fins.

8. The method of claim 1 , wherein said semiconductor structure is a semiconductor on insulator structure that includes a semiconductor layer in contact with an insulator layer.

9. The method of claim 8 , further comprising, after forming said one or more first isolation trenches and before forming said one or more second isolation trenches:

performing a first anneal to decrease the viscosity of said insulator layer.

10. The method of claim 9 , further comprising, after forming said one or more second isolation trenches:

performing a second anneal to further decrease the viscosity of said insulator material of said one or more first and second isolation trenches.

11. The method of claim 10 , wherein said first anneal has at least one of a temperature and duration that is greater than said second anneal.

12. The method of claim 10 , wherein:

said first anneal is performed at a temperature of between 1000° C. and 1150° C.; and

said second anneal is performed at a temperature of between 900 and 1000° C.

13. The method of claim 10 , wherein:

said first anneal is performed for a duration of between 30 and 90 minutes; and

said second anneal is performed for a duration of between 15 and 30 minutes.

14. The method of claim 10 , wherein the first material is boron or phosphor.

15. The method of claim 10 , further comprising forming the transistors in the semiconductor structure.

16. The method of claim 8 , further comprising, prior to forming said one or more first isolation trenches:

forming, in a surface of said semiconductor structure at least two initial trenches in said first direction;

introducing, via said at least two initial trenches, a stress in said semiconductor layer to provide said stressed semiconductor layer;

temporarily decreasing, by annealing, a viscosity of said insulator layer while maintaining the stress in said semiconductor layer; and

extending a depth of said at least two initial trenches to form said one or more first isolation trenches.

17. The method of claim 16 , wherein introducing a stress in said semiconductor layer comprises introducing a first material into said SOI structure via said at least two initial trenches, and wherein extending said at least two initial trenches comprises at least partially removing said first material.

18. The method of claim 17 , wherein introducing said first material comprises:

implanting atoms of said first material into a region of said semiconductor layer underlying each of said at least two initial trenches; or

depositing said first material to at least partially fill each of said at least two initial trenches.

19. A method comprising:

forming, in a semiconductor structure including a stressed semiconductor layer, a plurality of first isolation trenches in a first direction delimiting a first dimension of transistors to be formed in the semiconductor structure, the plurality of first isolation trenches extending into an insulating material having a viscosity;

forming, in the semiconductor structure, a plurality of second isolation trenches in a second direction delimiting a second dimension of the transistors, and

decreasing the viscosity of the insulating material in the plurality of first isolation trenches by implanting atoms of a first material into the plurality of first isolation trenches without implanting atoms of the first material into the plurality of second isolation trenches.

20. The method of claim 19 , wherein decreasing the viscosity of the insulating material in the plurality of first isolation trenches is performed before forming, in the semiconductor structure, a plurality of second isolation trenches in a second direction delimiting a second dimension of the transistors.

21. A method comprising:

forming, in a semiconductor structure including a stressed semiconductor layer, a plurality of first isolation trenches in a first direction delimiting a first dimension of transistors to be formed in the semiconductor structure;

forming, in the semiconductor structure, a plurality of second isolation trenches in a second direction delimiting a second dimension of the transistors,

at least partially filling the first and second isolation trenches with an insulating material having a viscosity;

decreasing the viscosity of the insulating material in the plurality of first isolation trenches by implanting atoms of a first material into the plurality of first isolation trenches without implanting atoms of the first material into the plurality of second isolation trenches; and

forming the transistors in the semiconductor structure.

22. The method of claim 21 , wherein each of the transistors are delimited by two of the first trenches and two of the second trenches.