IP Library Granted Patent US 9,926,187
Granted Patent B2
US 9,926,187 · App. 14/537,498 · Granted Mar 27, 2018

Microelectromechanical system devices having crack resistant membrane structures and methods for the fabrication thereof

Inventors: Chad S Dawson (Queen Creek, AZ); Dubravka Bilic (Scottsdale, AZ); Lianjun Liu (Chandler, AZ); Andrew C McNeil (Chandler, AZ)
Assignee: NXP USA, Inc.
B81B3/007G01L9/0072B81B2201/0264B81B2203/0127
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,926,187
App. No.
14/537,498
Granted
Mar 27, 2018
Kind
B2
Abstract

Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.

Claims (38)

1. A Microelectromechanical Systems (MEMS) device, comprising:

a substrate;

a multi-layer membrane structure formed on the substrate, the multi-layer membrane structure comprising:

a base membrane layer; and

a cap membrane layer formed over the base membrane layer and having outer edge regions, the cap membrane layer comprising a material having a substantially parallel grain orientation at the outer edge regions of the cap membrane layer, wherein the multi-layer membrane structure comprises, in cross-section, opposing anchor regions and a flexible diaphragm region extending between the opposing anchor regions; and

a cavity at least partially enclosed by the multi-layer membrane structure.

2. The MEMS device of claim 1 wherein the cap membrane layer and the base membrane layer each comprise polycrystalline silicon.

3. The MEMS device of claim 1 wherein a height of the multi-layer membrane structure is less than or equal to a width and a length thereof.

4. The MEMS device of claim 1 further comprising an electrode positioned beneath the flexible diaphragm region and exposed within the cavity, and wherein the cavity is hermetically sealed and contains a known reference pressure acting on an inner surface of the flexible diaphragm region.

5. The MEMS device of claim 1 wherein the anchor regions are formed by the base membrane layer, and wherein the flexible diaphragm region is formed by at least the cap membrane layer.

6. The MEMS device of claim 1 wherein the base membrane layer includes a region having a non-parallel grain orientation proximate an interface between the base membrane layer and the cap membrane layer, and wherein the cap membrane layer overlies the region of the base membrane layer having the non-parallel grain orientation.

7. The MEMS device of claim 1 further comprising:

a channel extending through the multi-layer membrane structure and to the cavity; and

a plug formed in the channel to hermetically seal the cavity.

8. The MEMS device of claim 7 wherein the channel extends through the base membrane layer and through the cap membrane layer.

9. The MEMS device of claim 7 wherein the channel extends through the cap membrane layer, but not through the base membrane layer.

10. The MEMS device of claim 1 wherein the base membrane layer has an upper planarized surface over which the cap membrane layer is deposited.

11. A Microelectromechanical Systems (MEMS) device, the MEMS device comprising:

a substrate;

a sense electrode on the substrate;

a sense dielectric layer over the sense electrode;

a multi-layer polysilicon membrane produced by forming multiple layers of polycrystalline silicon and planarizing at least one layer of polycrystalline silicon over which an additional layer of polycrystalline silicon is deposited such that at least an uppermost layer of the multi-layer polysilicon membrane is imparted with a substantially parallel grain structure, wherein the multi-layer polysilicon membrane comprises, in cross-section, opposing anchor regions and a flexible diaphragm region extending between the opposing anchor regions;

an inner cavity at least partially enclosed by the multi-layer polysilicon membrane;

at least one opening formed in the multi-layer polysilicon membrane and extending to the inner cavity;

a sealant material deposited into the at least one opening and hermetically sealing the inner cavity; and

a known reference pressure contained within the inner cavity to which the multi-layer polysilicon membrane is exposed.

12. The MEMS device of claim 11 wherein the uppermost layer of the multi-layer polysilicon membrane forms at least a portion of the flexible diaphragm region, while overlying the opposing anchor regions.

13. The MEMS device of claim 12 wherein the uppermost layer of the multi-layer polysilicon membrane forms the flexible diaphragm region in its substantial entirety.

14. The MEMS device of claim 11 wherein multi-layer polysilicon membrane comprises one or more peripheral corners, which are vertically aligned with the opposing anchor regions.

15. The MEMS device of claim 11 wherein the at least one layer of polycrystalline silicon that is planarized comprises a non-parallel grain region over which the additional layer of polycrystalline silicon is deposited.

16. A Microelectromechanical Systems (MEMS) device, the MEMS device comprising:

a substrate;

a multi-layer polysilicon membrane comprising:

a first polycrystalline silicon layer having an upper planarized surface and a non-parallel grain region; and

an uppermost polycrystalline silicon layer deposited over the upper planarized surface and overlying the non-parallel grain region of the first polycrystalline silicon layer, wherein the multi-layer polysilicon membrane comprises, in cross-section, opposing anchor regions and a flexible diaphragm region extending between the opposing anchor regions; and

an inner cavity at least partially enclosed by the multi-layer polysilicon membrane.

17. The MEMS device of claim 16 wherein the non-parallel grain region is located at an interface between the opposing anchor regions and the flexible diaphragm region.

18. The MEMS device of claim 16 wherein the first polycrystalline silicon layer includes the anchor regions joined to the substrate, and wherein the uppermost polycrystalline silicon layer comprises outer peripheral corner regions vertically aligned with the anchor regions and having a substantially parallel grain structure.

Assignments (12)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2026
From: NXP USA, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 075090/0783 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2014
From: DAWSON, CHAD S.; BILIC, DUBRAVKA; LIU, LIANJUN; MCNEIL, ANDREW C.
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 034143/0335 →
Continuity (3)
Division 13753034 · Jan 29, 2013
Related Publication 20150059484A1 · Mar 5, 2015
Related Publication 20170341926A9 · Nov 30, 2017