Three dimensional NAND device having reduced wafer bowing and method of making thereof

1. A monolithic three dimensional NAND memory device, comprising:

a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate, such that at least one first portion of each of the plurality of semiconductor channels is located in the first device level, and at least one second portion of each of the plurality of semiconductor channels is located in the second device level;

at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels; and

at least one first trench extending substantially perpendicular to the major surface of the substrate, the at least one first trench filled with at least a first trench material and a second trench material;

wherein trench further comprises an electrically insulating material located on the walls of the trench to electrically insulate the plurality of control gate electrodes from the first trench material; and

wherein the first trench material comprises a material under a first magnitude of a first stress type, and the second trench material comprises a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.

2. The monolithic three dimensional NAND memory device of claim 1 ,

wherein the first stress type is tensile stress and the first trench material comprises the material under first magnitude of tensile stress, and

wherein the second stress type is compressive stress and the second trench material comprises the material under compressive stress.

3. The monolithic three dimensional NAND memory device of claim 1 ,

wherein the first stress type is compressive stress and the first trench material comprises the material under first magnitude of compressive stress, and

wherein the second stress type is tensile stress and the second trench material comprises the material under tensile stress.

4. The monolithic three dimensional NAND memory device of claim 1 ,

wherein the first stress type is tensile stress and the first trench material comprises the material under first magnitude of tensile stress;

wherein the second stress type is compressive stress and the second trench material comprises a material under compressive stress; and

wherein the plurality of control gate electrodes are under tensile stress.

5. The monolithic three dimensional NAND memory device of claim 1 , wherein the first trench material comprises a plurality of electrically conductive pillars having a major axis substantially perpendicular to the major surface of the substrate.

6. The monolithic three dimensional NAND memory device of claim 5 , wherein the first trench material further comprises an electrically conductive layer contacting the plurality of pillars, wherein the electrically conductive layer is substantially parallel to the major surface of the substrate.

7. The monolithic three dimensional NAND memory device of claim 1 , wherein:

the plurality of control gate electrodes comprise an electrically conductive material;

the first trench material comprises an electrically conductive source electrode material contacting a source region in the substrate; and

the second trench material comprises an electrically insulating, electrically conductive, or semiconductor material.

8. The monolithic three dimensional NAND memory device of claim 7 , wherein:

the plurality of control gate electrodes comprise tungsten or a tungsten alloy;

the first trench material comprises tungsten or a tungsten alloy; and

the second trench material comprises a material selected from diamond-like carbon, N+ doped polycrystalline silicon, amorphous carbon, silicon carbide, silicon nitride, silicon oxynitride, and silicon carbonitride.

9. The monolithic three dimensional NAND memory device of claim 7 , wherein:

the plurality of control gate electrodes comprise tungsten or a tungsten alloy;

the first trench material comprises tungsten or a tungsten alloy; and

the second trench material comprises an air gap.

10. The monolithic three dimensional NAND memory device of claim 1 , wherein:

the first trench material comprises a plurality of electrically conductive pillars having a major axis substantially perpendicular to the major surface of the substrate; and

the second trench material is located between each of the plurality of electrically conductive pillars.

11. The monolithic three dimensional NAND memory device of claim 1 ,

wherein the semiconductor channel has a pillar shape and extends substantially perpendicular to the major surface of the substrate; and

further comprising one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above, and another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

12. The monolithic three dimensional NAND memory device of claim 1 , wherein:

the semiconductor channel has J-shaped pipe shape;

a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate;

a source region and a drain region each contact the semiconductor channel;

a drain electrode contacts the drain region in the first wing portion of the semiconductor channel from above; and

the first trench material comprises a pillar shaped source electrode which contacts the source region in the connecting portion of the semiconductor channel from above.

13. The monolithic three dimensional NAND memory device of claim 11 , further comprising:

a rail shaped source line which electrically contacts an electrode shunt and the source electrode, wherein:

the source line is located in the trench, and

the source line extends substantially parallel to the plurality of control gate electrodes; and

a bit line which is electrically connected to the drain electrode, wherein the bit line is located above the semiconductor channel, and the bit line extends substantially perpendicular to the plurality of control gate electrodes and to the source line.

14. A monolithic three dimensional NAND memory device, comprising:

a silicon substrate;

an array of monolithic three dimensional NAND strings having a plurality of device levels disposed above the silicon substrate; and

a driver circuit associated with the array located above or in the silicon substrate;

wherein each monolithic three dimensional NAND string of the array of monolithic three dimensional NAND strings comprises:

a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate, such that at least one first portion of each of the plurality of semiconductor channels is located in the first device level, and at least one second portion of each of the plurality of semiconductor channels is located in the second device level;

at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels; and

at least one first trench extending substantially perpendicular to the major surface of the substrate, the at least one first trench filled with at least a first trench material and a second trench material;

wherein the first trench material comprises a plurality of electrically conductive pillars having a major axis substantially perpendicular to the major surface of the substrate, and

wherein the first trench material comprises a material under a first magnitude of a first stress type, and the second trench material comprises a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate.