Display device and electronic device including the same
It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.
1. A semiconductor device comprising:
a first transistor, a second transistor, and a third transistor each including a gate, a first terminal, and a second terminal;
a first capacitor and a second capacitor each including a first electrode and a second electrode; and
a first wiring and a second wiring,
wherein the gate of the first transistor is electrically connected to the first terminal of the second transistor,
wherein the gate of the first transistor is electrically connected to the gate of the third transistor,
wherein the gate of the first transistor is electrically connected to the first electrode of the first capacitor,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein the second terminal of the first transistor is electrically connected to the second electrode of the first capacitor,
wherein the gate of the second transistor is electrically connected to the first terminal of the third transistor,
wherein the second terminal of the second transistor is electrically connected to the second wiring,
wherein the first terminal of the third transistor is electrically connected to the first electrode of the second capacitor,
wherein the second terminal of the third transistor is electrically connected to the second wiring, and
wherein the second electrode of the second capacitor is electrically connected to the first wiring.
2. The semiconductor device according to claim 1 , wherein each semiconductor layer of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor layer.
3. The semiconductor device according to claim 1 , wherein a channel width of the first transistor is larger than a channel width of each of the second transistor and the third transistor.
4. The semiconductor device according to claim 1 , further comprising:
a diode,
wherein the diode is electrically connected to the first wiring, and
wherein the diode is electrically connected to the first electrode of the second capacitor.
5. The semiconductor device according to claim 1 , further comprising:
a fourth transistor including a gate, a first terminal, and a second terminal,
wherein the gate of the fourth transistor is electrically connected to the first electrode of the second capacitor,
wherein the first terminal of the fourth transistor is electrically connected to the first wiring, and
wherein the second terminal of the fourth transistor is electrically connected to the first electrode of the second capacitor.
6. A semiconductor device comprising:
a first transistor, a second transistor, and a third transistor each including a gate, a first terminal, and a second terminal;
a first capacitor and a second capacitor each including a first electrode and a second electrode; and
a first wiring and a second wiring,
wherein the gate of the first transistor is electrically connected to the first terminal of the second transistor,
wherein the gate of the first transistor is electrically connected to the gate of the third transistor,
wherein the gate of the first transistor is electrically connected to the first electrode of the first capacitor,
wherein the first terminal of the first transistor is electrically connected to the first wiring,
wherein the second terminal of the first transistor is electrically connected to the second terminal of the second transistor,
wherein the second terminal of the first transistor is electrically connected to the second electrode of the first capacitor,
wherein the gate of the second transistor is electrically connected to the first wiring,
wherein the first terminal of the third transistor is electrically connected to the second wiring,
wherein the second terminal of the third transistor is electrically connected to the first electrode of the second capacitor, and
wherein the second electrode of the second capacitor is electrically connected to the first wiring.
7. The semiconductor device according to claim 6 , further comprising:
a fourth transistor including a gate, a first terminal, and a second terminal,
wherein the gate of the fourth transistor is electrically connected to the second terminal of the third transistor,
wherein the first terminal of the fourth transistor is electrically connected to the second wiring, and
wherein the second terminal of the fourth transistor is electrically connected to the second terminal of the first transistor.
8. The semiconductor device according to claim 6 , wherein each semiconductor layer of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor layer.
9. The semiconductor device according to claim 6 , wherein a channel width of the first transistor is larger than a channel width of each of the second transistor and the third transistor.
10. The semiconductor device according to claim 6 , further comprising:
a diode,
wherein the diode is electrically connected to the first wiring, and
wherein the diode is electrically connected to the first electrode of the second capacitor.
11. The semiconductor device according to claim 6 , further comprising:
a fourth transistor including a gate, a first terminal, and a second terminal,
wherein the gate of the fourth transistor is electrically connected to the first electrode of the second capacitor,
wherein the first terminal of the fourth transistor is electrically connected to the first wiring, and
wherein the second terminal of the fourth transistor is electrically connected to the first electrode of the second capacitor.