Three-dimensional memory structure having a back gate electrode
A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
1. A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:
applying a positive voltage to the back gate electrode; and
applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string,
wherein an absolute value of the positive voltage applied to the back gate electrode is smaller than an absolute value of the negative read voltage applied to the selected control gate electrode.
2. The method of claim 1 , further comprising applying a voltage between a source and a drain of the NAND string.
3. A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:
applying a positive voltage to the back gate electrode;
applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
applying a voltage between a source and a drain of the NAND string; and
determining that charge is stored in a charge storage region of the memory film of the selected cell if no current flows between the source and the drain during application of the positive voltage to the back gate electrode and the negative read voltage of the selected control gate electrode.
4. A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:
applying a positive voltage to the back gate electrode;
applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
applying a voltage between a source and a drain of the NAND string; and
determining that no charge is stored in a charge storage region of the memory film of the selected cell if current flows between the source and the drain during application of the positive voltage to the back gate electrode and the negative read voltage of the selected control gate electrode.
5. A method of reading a three dimensional NAND string comprising a semiconductor channel having at least one vertical portion, a plurality of vertically separated control gate electrodes, a memory film located between a first side of the vertical portion of the semiconductor channel and the control gate electrodes, a back gate electrode, and a back gate dielectric located between a second side of the vertical portion of the semiconductor channel and the back gate electrode, the method comprising:
applying a positive voltage to the back gate electrode;
applying a negative read voltage to a selected control gate electrode to read a selected cell of the NAND string;
applying a voltage between a source and a drain of the NAND string;
applying a first pair of electrical bias conditions comprising applying a first backside bias voltage to the back gate electrode and a first control gate bias voltage to the control gate electrode of the selected cell;
applying a second pair of electrical bias conditions comprising applying a second backside bias voltage to the back gate electrode and a second control gate bias voltage to the control gate electrode of the selected cell, wherein:
(i) the first and the second backside bias voltages are the same and the first and the second control gate bias voltages are different, or
(ii) the first and the second backside bias voltages are different and the first and the second control gate bias voltages are the same; and
determining a total amount of electrical charge stored in a charge storage region of the memory film of the selected cell when an electrical current through the semiconductor channel is above a predefined threshold level for the first pair of electrical bias conditions, and is below a predefined threshold level for the second pair of electrical bias conditions.