Selective blocking dielectric formation in a three-dimensional memory structure
A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.
1. A monolithic three-dimensional NAND memory device, comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a substrate;
a memory opening extending through the stack of alternating layers;
a lateral stack located within the memory opening and comprising, from outside to inside, a memory film and a semiconductor channel; and
a plurality of blocking dielectric portions vertically spaced from each other, comprising a dielectric metal oxide having a dielectric constant greater than 7.9, and contacting a respective portion of an outer sidewall of the memory film and a sidewall of a respective electrically conductive layer.
2. The monolithic three-dimensional NAND memory device of claim 1 , wherein each of the plurality of blocking dielectric portions contacts at least one horizontal surface of the insulator layers.
3. The monolithic three-dimensional NAND memory device of claim 1 , wherein the plurality of blocking dielectric portions comprise a material that is different from a material of the insulator layers.
4. The monolithic three-dimensional NAND memory device of claim 1 , wherein:
the memory film comprises a memory material layer and a tunneling dielectric layer;
the plurality of blocking dielectric portions contacts an outer sidewall of the memory material layer; and
the plurality of blocking dielectric portions comprises a material that is different from a material of the memory material layer.
5. The monolithic three-dimensional NAND memory device of claim 4 , wherein a material of the memory material layer has a hydrophobicity that is different from a hydrophobicity of a material of the insulator layers.
6. The monolithic three-dimensional NAND memory device of claim 1 , further comprising a plurality of dielectric material portions that are vertically spaced apart, comprising a different material than the plurality of blocking dielectric portions, and contacting an overlying blocking dielectric portion and an underlying blocking dielectric portion.
7. The monolithic three-dimensional NAND memory device of claim 6 , wherein each of the plurality of dielectric material portions contact a sidewall of a respective insulator layer.
8. The monolithic three-dimensional NAND memory device of claim 6 , wherein a dielectric material portion among the plurality of dielectric material portions has a lesser vertical extent than one of the insulator layers that contacts the dielectric material portion.
9. The monolithic three-dimensional NAND memory device of claim 6 , wherein a blocking dielectric portion among the plurality of blocking dielectric portions has a greater vertical extent than one of the electrically conductive layers that contacts the blocking dielectric portion.
10. The monolithic three-dimensional NAND memory device of claim 6 , wherein the plurality of dielectric material portions and the plurality of blocking dielectric portions constitute an alternating stack of annular structures.
11. The monolithic three-dimensional NAND memory device of claim 1 , wherein an outer sidewall of one of the plurality of blocking dielectric portions contacts an sidewall of one of the insulator layers.
12. The monolithic three-dimensional NAND memory device of claim 1 , wherein the memory film comprises, from outside to inside, a blocking dielectric layer, a memory material layer, and a tunneling dielectric layer.
13. The monolithic three-dimensional NAND memory device of claim 12 , wherein the plurality of blocking dielectric portions comprise a material that is different from a material of the blocking dielectric layer.
14. The monolithic three-dimensional NAND memory device of claim 12 , wherein a material of the blocking dielectric layer has a hydrophobicity that is different from a hydrophobicity of a material of the insulator layers.
15. The monolithic three-dimensional NAND memory device of claim 12 , wherein the blocking dielectric layer comprises silicon nitride, and the insulator layers comprise silicon oxide.
16. The monolithic three-dimensional NAND memory device of claim 15 , further comprising an inner blocking dielectric layer contacting the blocking dielectric layer and the memory material layer.
17. The monolithic three-dimensional NAND memory device of claim 12 , wherein the blocking dielectric layer is a contiguous layer that extends through an entirety of the stack of alternating layers, and each of the plurality of blocking dielectric portions contacts a portion of an outer sidewall of the blocking dielectric layer.
18. The monolithic three-dimensional NAND memory device of claim 17 , wherein outer sidewalls of the plurality of blocking dielectric portions are laterally spaced farther away from the memory material layer than an outer sidewall of the blocking dielectric layer.
19. The monolithic three-dimensional NAND memory device of claim 17 , wherein outer sidewalls of the plurality of blocking dielectric portions are laterally spaced by a same distance from the memory material layer as an outer sidewall of the blocking dielectric layer.
20. The monolithic three-dimensional NAND memory device of claim 19 , wherein the blocking dielectric layer and the memory material layer have undulating inner sidewalls having a variable lateral distance from a vertical sidewall of the memory opening as a function of a height from a top surface of the substrate.
21. The monolithic three-dimensional NAND memory device of claim 1 , wherein each of the plurality of blocking dielectric portions comprises a vertical portion, an upper laterally-protruding portion that protrudes outward from an outer sidewall of the vertical portion, and a lower laterally-protruding portion that protrudes outward from the outer sidewall of the vertical portion.
22. The monolithic three-dimensional NAND memory device of claim 1 , wherein the plurality of blocking dielectric portions comprises aluminum oxide and the insulator layers comprise silicon oxide.
23. The monolithic three-dimensional NAND memory device of claim 1 , wherein the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND memory device.
24. The monolithic three-dimensional NAND memory device of claim 14 , wherein:
the substrate comprises a silicon substrate;
the NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
each NAND string comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.