IP Library Granted Patent US 9,906,249
Granted Patent B2
US 9,906,249 · App. 14/572,778 · Granted Feb 27, 2018

Method and apparatus for compensating for a loss of low-frequency signal content of an input signal at a receiver input

Inventors: Mirembe A. Musisi-Nkambwe (Chandler, AZ); Martin J. Bayer (Gilbert, AZ); Jeffrey A. Porter (Gilbert, AZ)
Assignee: NXP USA, Inc.
H04B1/16H04L25/10H04L43/16
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Quick Facts
Patent No.
US 9,906,249
App. No.
14/572,778
Granted
Feb 27, 2018
Kind
B2
Abstract

A compensation circuit is configured to compensate for a loss of low-frequency signal content of an input signal at a receiver input. The compensation circuit includes a switching circuit and a summing circuit coupled to the switching circuit. The switching circuit is configured to receive a first plurality of digitized values sampled from a receiver output signal. The summing circuit is configured to generate a summation signal based on a combination of a first plurality of input values selected by the switching circuit. The selecting is based on the first plurality of digitized values. The compensation circuit is configured to provide to the receiver input a compensation signal to compensate for the loss of the low-frequency signal content from the input signal. The compensation signal is based on the summation signal and is a function of at least one gain value.

Claims (34)

1. A compensation circuit configured to compensate for a loss of low-frequency signal content of an input signal at a receiver input, the compensation circuit comprising:

a switching circuit configured to receive a first plurality of digitized values sampled from a receiver output signal;

a summing circuit coupled to the switching circuit, wherein the summing circuit comprises an averager circuit configured to generate a summation signal based on an average of a first plurality of input values selected by the switching circuit, wherein the selecting is based on the first plurality of digitized values;

wherein the compensation circuit is configured to provide to the receiver input a compensation signal to compensate for the loss of the low-frequency signal content from the input signal, wherein the compensation signal is based on the summation signal and is a function of at least one gain value.

2. The compensation circuit of claim 1 , wherein the averager circuit comprises a passive summing circuit.

3. The compensation circuit of claim 2 , wherein the passive summing circuit comprises a plurality of resistor networks coupled in parallel between the switching circuit and the receiver input.

4. The compensation circuit of claim 1 , wherein a number of connections into the summing circuit for receiving the plurality of input values is the same as the number of digitized values in the plurality of digitized values.

5. The compensation circuit of claim 1 :

wherein the summing circuit is coupled through the switching circuit to a gain circuit that is configured to provide multiple gain values, wherein the switching circuit is configured to select a portion of the multiple gain values as the first plurality of input values to provide to the summing circuit to generate the summation signal;

wherein the summing circuit is configured to generate the summation signal as the compensation signal based on a combination of the selected portion of the multiple gain values.

6. The compensation circuit of claim 1 further comprising a compensation enablement circuit coupled between the summing circuit and the receiver input, wherein the compensation enablement circuit is configured to control, based on the summation signal, whether or not to provide the compensation signal to the receiver input.

7. The compensation circuit of claim 6 , wherein the compensation enablement circuit comprises:

a comparison circuit coupled to the summing circuit, wherein the comparison circuit is configured to receive the summation signal to use in generating a control signal; and

a gain selection circuit coupled to the comparison circuit, wherein the gain selection circuit is configured to receive the control signal to use in:

enabling or disabling a connection for providing the compensation signal;

selecting one of a plurality of full amplitude gain values to provide as the compensation signal to the receiver input.

8. The compensation circuit of claim 7 , wherein the comparison circuit comprises a first comparator and a second comparator coupled between the summing circuit and the gain selection circuit, wherein the first and second comparators are configured with different threshold trip points to use in adjusting the control signal based on the summation signal.

9. The compensation circuit of claim 1 , wherein the switching circuit is coupled to a sampler circuit that is configured to provide the first plurality of digitized values at multiple phases.

10. The compensation circuit of claim 1 further comprising a filter coupled to the receiver input, wherein the filter is configured to operate as a high pass filter for the input signal and is configured to operate as a low pass filter for the compensation signal.

11. The compensation circuit of claim 1 , wherein a sampler circuit that provides the plurality of digitized values, the switching circuit, and the summing circuit are configured to operate as a low pass filter for the compensation signal.

12. A method for compensating for a loss of low-frequency signal content of an input signal at a receiver input, the method comprising:

receiving a first plurality of digitized values sampled from a receiver output signal;

selecting a first plurality of input values, wherein the selecting is based on the first plurality of digitized values;

generating a summation signal based on an average of the first plurality of input values;

generating a compensation signal to provide at the receiver input to compensate for the loss of the low-frequency signal content from the input signal, wherein the compensation signal is based on the summation signal and is a function of at least one gain value.

13. The method of claim 12 , wherein the first plurality of digitized values is received at multiple phases, and the summation signal comprises a moving average of the plurality of input values determined as each input value is received.

14. The method of claim 13 , wherein the input signal is characterized by a first frequency, f1, and wherein the selecting of the first plurality of input values is characterized by a second frequency of f1/N, where N is a number of digitized values in the plurality of received digitized values.

15. The method of claim 12 , wherein the plurality of input values comprises a plurality of gain values, and wherein the compensation signal is the summation signal, which is based on an average of the plurality of gain values.

16. The method of claim 12 further comprising filtering the compensation signal using a filter that is also used to filter the input signal.

17. The method of claim 12 , wherein generating the compensation signal comprises:

comparing the summation signal to at least one threshold value to generate a control signal;

determining, based on the control signal, whether or not to provide the compensation signal to the receiver input.

18. The method of claim 17 , wherein generating the compensation signal further comprises selecting, based on the control signal, one of a plurality of full amplitude gain values as the compensation signal, when it is determined to provide the compensation signal to the receiver input.

19. The method of claim 17 , wherein comparing the summation signal to the at least one threshold value to generate the control signal comprises comparing the summation signal to a first threshold value set for a first comparator and comparing the summation signal to a second threshold value set for a second comparator.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2014
From: MUSISI-NKAMBWE, MIREMBE A.; BAYER, MARTIN J.; PORTER, JEFFREY A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034522/0581 →
Continuity (1)
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