Offset-cancelling self-reference STT-MRAM sense amplifier
View Patent ↗Embodiments are directed to a self-reference STT-MRAM sensing scheme that uses offset-cancellation to reduce the impact of FET mismatch and thereby allow the sensing of lower read voltages. In some embodiments, the sensing scheme includes a differential amplifier having a first input connected to a memory cell. In some embodiments, a second input of the differential amplifier may be connected to ground, a common mode voltage of the system or a mid-level supply voltage. The present disclosure provides flexibility with respect to the voltage level at which the sensing is performed (e.g., ground, Voc, Vmid, etc.). The present disclosure provides further flexibility with respect to the sense voltage polarity.
1. A sense amplifier comprising:
a first differential amplifier including a first input, a second input, a first output and a first voltage offset;
wherein said first input is coupled to a memory cell via a first capacitive element;
wherein said second input is coupled to ground via a second capacitive element;
wherein said first output of said differential amplifier is coupled to a comparator via a second differential amplifier including a third input, a fourth input, a second output and a second voltage offset;
said memory cell including a read state, a write state and a data state; and
read/write circuitry coupled to said memory cell and capable of reading or writing said data state of said memory cell;
wherein said read/write circuitry further comprises:
a sense data phase wherein said read/write circuitry reads said data state;
a write reference phase wherein said read/write circuitry writes said data state to a first reference state and a second reference state; and
a sense reference phase wherein said read/write circuitry reads said second reference state;
wherein said first differential amplifier senses said data state by sensing a first difference between said first input and said second input, canceling said first voltage offset and amplifying said first difference;
wherein said first differential amplifier senses a second difference between said data state and said second reference state to thereby determine a polarity of said data state;
wherein said third input is coupled to said first output of said first differential amplifier, and said fourth input is coupled to said second output of said first differential amplifier;
wherein said third input is coupled to said first output of said first differential amplifier via said second capacitive element;
wherein said fourth input is coupled to said second output of said first differential amplifier via a third capacitive element; and
wherein said second differential amplifier cancels said second offset voltage and further amplifies said second difference.
2. The sense amplifier of claim 1 wherein said first differential amplifier comprises a closed loop.
3. The sense amplifier of claim 1 wherein said second input of said first differential amplifier is coupled to a common mode voltage.
4. The sense amplifier of claim 1 wherein said second input of said first differential amplifier is coupled to a mid-level supply voltage.
5. The sense amplifier of claim 1 wherein said memory cell comprises a spin transfer torque magnetic random access memory (STT-MRAM).
6. A method of sensing a data state of a memory cell, the method comprising:
reading a data state of the memory cell;
writing said data state of the memory cell to a first reference state and a second reference state; and
reading said second reference state of the cell;
wherein the memory cell is coupled to a first input of a first differential amplifier having a first voltage offset, and wherein said first differential amplifier senses the data state by sensing a first difference between said first input and said second input, canceling said first voltage offset and amplifying said first difference;
wherein said first input of said first differential amplifier is coupled to said memory cell via a first capacitive element;
wherein said second input of said first differential amplifier is coupled to a ground via a second capacitive element;
wherein said first differential amplifier senses a second difference between said data state and said second reference state to thereby determine a polarity of said data state;
wherein said first differential amplifier comprises a closed loop;
wherein said first output of said first differential amplifier is coupled to a comparator;
wherein said first output of said first differential amplifier is coupled to said comparator via a second differential amplifier including a third input, a fourth input, a second output, and a second voltage offset;
wherein said third input is coupled to said first output of said first differential amplifier;
wherein said fourth input is coupled to said second output of said first differential amplifier;
wherein said third input is coupled to said first output of said first differential amplifier via said second capacitive element;
wherein said fourth input is coupled to said second output of said first differential amplifier via a third capacitive element; and
wherein said second differential amplifier cancels said second offset voltage and further amplifies said second difference.
7. The method of claim 6 wherein said second input of said first differential amplifier is coupled to a common mode voltage.
8. The method of claim 6 wherein said second input of said first differential amplifier is coupled to a mid-level supply voltage.
9. The method of claim 6 wherein the memory cell comprises a spin transfer torque magnetic random access memory (STT-MRAM).
10. The method of claim 9 wherein said STT-RAM comprises a mesh configuration.