Method for forming metal oxides and silicides in a memory device
View Patent ↗Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
1. A semiconductor device comprising:
a lower electrode comprising silicon;
a metal silicide layer disposed over the lower electrode;
a metal oxide layer disposed over the metal silicide layer,
wherein the metal silicide layer and the metal oxide layer comprise a common metal,
wherein the common metal comprises hafnium, zirconium, or both,
wherein the metal silicide layer comprises a dopant, and
wherein the metal oxide layer is configured to resistively switch between a first resistive state and a second resistive state different from the first resistive state; and
an upper electrode disposed over the metal oxide layer.
2. The semiconductor device of claim 1 , wherein the common metal comprises hafnium.
3. The semiconductor device of claim 1 , wherein the common metal comprises hafnium and zirconium.
4. The semiconductor device of claim 1 , wherein the metal oxide layer has a thickness of 20 Angstroms and 80 Angstroms.
5. The semiconductor device of claim 1 , wherein the silicon of the lower electrode is polycrystalline silicon.
6. The semiconductor device of claim 5 , wherein the polycrystalline silicon of the lower electrode is n-type polysilicon.
7. The semiconductor device of claim 1 , wherein the metal silicide layer has a thickness of 5 Angstroms and 40 Angstroms.
8. The semiconductor device of claim 1 , wherein the metal silicide layer has a thickness of 8 Angstroms and 25 Angstroms.
9. The semiconductor device of claim 1 , wherein the metal silicide layer has a thickness of 10 Angstroms and 20 Angstroms.
10. The semiconductor device of claim 1 , wherein the lower electrode comprises a dopant.
11. The semiconductor device of claim 10 , wherein the dopant in the lower electrode has a concentration of between 1 atomic % and 4 atomic %.
12. The semiconductor device of claim 10 , wherein the dopant in the lower electrode has a concentration of between 2 atomic % and 3 atomic %.
13. The semiconductor device of claim 10 , wherein the dopant is fluorine.
14. The semiconductor device of claim 13 , wherein an interface of the metal oxide layer and the metal silicide layer comprises fluorine.
15. The semiconductor device of claim 1 , wherein a work function of the lower electrode is different from a work function of the upper electrode by at least 0.4 eV and 0.6 eV.
16. The semiconductor device of claim 1 , wherein the upper electrode comprises titanium nitride.
17. The semiconductor device of claim 1 , wherein the metal silicide layer directly interfaces the lower electrode.
18. The semiconductor device of claim 17 , wherein the metal oxide layer directly interfaces the metal silicide layer.
19. The semiconductor device of claim 1 , wherein the metallic oxide layer comprises a dopant, the dopant comprising one of aluminum, yttrium, scandium, or gadolinium.
20. The semiconductor device of claim 1 , wherein the dopant is aluminum.